drm/i915/skl: Add WAC6entrylatency
This workaround is for fbc working with rc6 on skylake. Bspec states that setting this bit needs to be coordinated with uncore but offers no further details. v2: rebase References: HSD#4712857 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-18-git-send-email-mika.kuoppala@intel.com
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@ -2167,6 +2167,9 @@ enum skl_disp_power_wells {
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#define FBC_LL_SIZE (1536)
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#define FBC_LL_SIZE (1536)
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#define FBC_LLC_READ_CTRL _MMIO(0x9044)
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#define FBC_LLC_FULLY_OPEN (1<<30)
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/* Framebuffer compression for GM45+ */
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/* Framebuffer compression for GM45+ */
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#define DPFC_CB_BASE _MMIO(0x3200)
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#define DPFC_CB_BASE _MMIO(0x3200)
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#define DPFC_CONTROL _MMIO(0x3208)
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#define DPFC_CONTROL _MMIO(0x3208)
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@ -6992,7 +6992,13 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
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static void skylake_init_clock_gating(struct drm_device *dev)
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static void skylake_init_clock_gating(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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gen9_init_clock_gating(dev);
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gen9_init_clock_gating(dev);
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/* WAC6entrylatency:skl */
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I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
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FBC_LLC_FULLY_OPEN);
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}
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}
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static void broadwell_init_clock_gating(struct drm_device *dev)
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static void broadwell_init_clock_gating(struct drm_device *dev)
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