KVM: x86/mmu: Set SPTE_AD_WRPROT_ONLY_MASK if and only if PML is enabled
Check that PML is actually enabled before setting the mask to force a
SPTE to be write-protected. The bits used for the !AD_ENABLED case are
in the upper half of the SPTE. With 64-bit paging and EPT, these bits
are ignored, but with 32-bit PAE paging they are reserved. Setting them
for L2 SPTEs without checking PML breaks NPT on 32-bit KVM.
Fixes: 1f4e5fc83a
("KVM: x86: fix nested guest live migration with PML")
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210225204749.1512652-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
919f4ebc59
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@ -81,15 +81,15 @@ static inline struct kvm_mmu_page *sptep_to_sp(u64 *sptep)
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static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu)
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{
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/*
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* When using the EPT page-modification log, the GPAs in the log
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* would come from L2 rather than L1. Therefore, we need to rely
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* on write protection to record dirty pages. This also bypasses
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* PML, since writes now result in a vmexit. Note, this helper will
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* tag SPTEs as needing write-protection even if PML is disabled or
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* unsupported, but that's ok because the tag is consumed if and only
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* if PML is enabled. Omit the PML check to save a few uops.
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* When using the EPT page-modification log, the GPAs in the CPU dirty
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* log would come from L2 rather than L1. Therefore, we need to rely
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* on write protection to record dirty pages, which bypasses PML, since
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* writes now result in a vmexit. Note, the check on CPU dirty logging
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* being enabled is mandatory as the bits used to denote WP-only SPTEs
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* are reserved for NPT w/ PAE (32-bit KVM).
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*/
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return vcpu->arch.mmu == &vcpu->arch.guest_mmu;
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return vcpu->arch.mmu == &vcpu->arch.guest_mmu &&
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kvm_x86_ops.cpu_dirty_log_size;
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}
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bool is_nx_huge_page_enabled(void);
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