arm64: mm: Add additional parameter to uaccess_ttbr0_enable
Add an extra temporary register parameter to uaccess_ttbr0_enable which
is about to be required for arm64 PAN support.
This patch doesn't introduce any functional change but ensures that the
kernel compiles once the KVM/ARM tree is merged with the arm64 tree by
ensuring a trivially mergable conflict with commit
27a921e757
("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN").
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
This commit is contained in:
parent
17ab9d57de
commit
448fadc8a4
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@ -31,7 +31,7 @@ alternative_if_not ARM64_HAS_PAN
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alternative_else_nop_endif
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.endm
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.macro uaccess_ttbr0_enable, tmp1, tmp2
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.macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
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alternative_if_not ARM64_HAS_PAN
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save_and_disable_irq \tmp2 // avoid preemption
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__uaccess_ttbr0_enable \tmp1
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@ -42,7 +42,7 @@ alternative_else_nop_endif
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.macro uaccess_ttbr0_disable, tmp1
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.endm
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.macro uaccess_ttbr0_enable, tmp1, tmp2
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.macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
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.endm
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#endif
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@ -49,7 +49,7 @@ ENTRY(flush_icache_range)
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* - end - virtual end address of region
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*/
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ENTRY(__flush_cache_user_range)
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uaccess_ttbr0_enable x2, x3
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uaccess_ttbr0_enable x2, x3, x4
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dcache_line_size x2, x3
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sub x3, x2, #1
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bic x4, x0, x3
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@ -80,7 +80,7 @@ ENDPROC(__flush_cache_user_range)
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* - end - virtual end address of region
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*/
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ENTRY(invalidate_icache_range)
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uaccess_ttbr0_enable x2, x3
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uaccess_ttbr0_enable x2, x3, x4
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invalidate_icache_by_line x0, x1, x2, x3, 2f
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mov x0, xzr
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@ -101,7 +101,7 @@ ENTRY(privcmd_call)
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* need the explicit uaccess_enable/disable if the TTBR0 PAN emulation
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* is enabled (it implies that hardware UAO and PAN disabled).
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*/
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uaccess_ttbr0_enable x6, x7
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uaccess_ttbr0_enable x6, x7, x8
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hvc XEN_IMM
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/*
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