[media] v4l: ti-vpe: create a scaler block library
VPE and VIP IPs in DAR7x contain a scaler(SC) sub block. Create a library which will perform scaler block related configurations and hold SC register definitions. The functions provided by this library will be called by the vpe and vip drivers using a sc_data handle. The vpe_dev holds the sc_data handle. The handle represents an instance of the SC hardware, and the vpe driver uses it to access the scaler register offsets or helper functions to configure these registers. We move the SC register definitions to sc.h so that they aren't specific to VPE anymore. The register offsets are now relative to the sub-block, and not the VPE IP as a whole. In order for VPDMA to configure registers, it requires it's offset from the top level VPE module. A macro called GET_OFFSET_TOP is added to return the offset of the register relative to the VPE IP. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Archit Taneja
Mauro Carvalho Chehab
parent
aa32f4c0bc
commit
44687b2e81
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@ -1,5 +1,5 @@
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obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o
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ti-vpe-y := vpe.o vpdma.o
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ti-vpe-y := vpe.o sc.o vpdma.o
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ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG
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@ -0,0 +1,91 @@
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/*
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* Scaler library
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*
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* Copyright (c) 2013 Texas Instruments Inc.
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*
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* David Griego, <dagriego@biglakesoftware.com>
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* Dale Farnsworth, <dale@farnsworth.org>
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* Archit Taneja, <archit@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "sc.h"
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void sc_set_regs_bypass(struct sc_data *sc, u32 *sc_reg0)
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{
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*sc_reg0 |= CFG_SC_BYPASS;
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}
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void sc_dump_regs(struct sc_data *sc)
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{
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struct device *dev = &sc->pdev->dev;
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u32 read_reg(struct sc_data *sc, int offset)
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{
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return ioread32(sc->base + offset);
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}
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#define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(sc, CFG_##r))
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DUMPREG(SC0);
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DUMPREG(SC1);
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DUMPREG(SC2);
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DUMPREG(SC3);
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DUMPREG(SC4);
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DUMPREG(SC5);
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DUMPREG(SC6);
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DUMPREG(SC8);
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DUMPREG(SC9);
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DUMPREG(SC10);
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DUMPREG(SC11);
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DUMPREG(SC12);
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DUMPREG(SC13);
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DUMPREG(SC17);
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DUMPREG(SC18);
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DUMPREG(SC19);
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DUMPREG(SC20);
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DUMPREG(SC21);
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DUMPREG(SC22);
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DUMPREG(SC23);
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DUMPREG(SC24);
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DUMPREG(SC25);
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#undef DUMPREG
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}
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struct sc_data *sc_create(struct platform_device *pdev)
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{
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struct sc_data *sc;
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dev_dbg(&pdev->dev, "sc_create\n");
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sc = devm_kzalloc(&pdev->dev, sizeof(*sc), GFP_KERNEL);
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if (!sc) {
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dev_err(&pdev->dev, "couldn't alloc sc_data\n");
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return ERR_PTR(-ENOMEM);
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}
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sc->pdev = pdev;
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sc->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sc");
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if (!sc->res) {
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dev_err(&pdev->dev, "missing platform resources data\n");
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return ERR_PTR(-ENODEV);
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}
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sc->base = devm_ioremap_resource(&pdev->dev, sc->res);
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if (!sc->base) {
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dev_err(&pdev->dev, "failed to ioremap\n");
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return ERR_PTR(-ENOMEM);
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}
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return sc;
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}
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@ -0,0 +1,175 @@
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/*
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* Copyright (c) 2013 Texas Instruments Inc.
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*
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* David Griego, <dagriego@biglakesoftware.com>
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* Dale Farnsworth, <dale@farnsworth.org>
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* Archit Taneja, <archit@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#ifndef TI_SC_H
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#define TI_SC_H
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/* Scaler regs */
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#define CFG_SC0 0x0
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#define CFG_INTERLACE_O (1 << 0)
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#define CFG_LINEAR (1 << 1)
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#define CFG_SC_BYPASS (1 << 2)
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#define CFG_INVT_FID (1 << 3)
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#define CFG_USE_RAV (1 << 4)
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#define CFG_ENABLE_EV (1 << 5)
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#define CFG_AUTO_HS (1 << 6)
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#define CFG_DCM_2X (1 << 7)
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#define CFG_DCM_4X (1 << 8)
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#define CFG_HP_BYPASS (1 << 9)
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#define CFG_INTERLACE_I (1 << 10)
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#define CFG_ENABLE_SIN2_VER_INTP (1 << 11)
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#define CFG_Y_PK_EN (1 << 14)
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#define CFG_TRIM (1 << 15)
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#define CFG_SELFGEN_FID (1 << 16)
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#define CFG_SC1 0x4
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#define CFG_ROW_ACC_INC_MASK 0x07ffffff
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#define CFG_ROW_ACC_INC_SHIFT 0
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#define CFG_SC2 0x08
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#define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
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#define CFG_ROW_ACC_OFFSET_SHIFT 0
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#define CFG_SC3 0x0c
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#define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
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#define CFG_ROW_ACC_OFFSET_B_SHIFT 0
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#define CFG_SC4 0x10
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#define CFG_TAR_H_MASK 0x07ff
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#define CFG_TAR_H_SHIFT 0
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#define CFG_TAR_W_MASK 0x07ff
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#define CFG_TAR_W_SHIFT 12
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#define CFG_LIN_ACC_INC_U_MASK 0x07
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#define CFG_LIN_ACC_INC_U_SHIFT 24
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#define CFG_NLIN_ACC_INIT_U_MASK 0x07
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#define CFG_NLIN_ACC_INIT_U_SHIFT 28
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#define CFG_SC5 0x14
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#define CFG_SRC_H_MASK 0x07ff
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#define CFG_SRC_H_SHIFT 0
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#define CFG_SRC_W_MASK 0x07ff
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#define CFG_SRC_W_SHIFT 12
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#define CFG_NLIN_ACC_INC_U_MASK 0x07
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#define CFG_NLIN_ACC_INC_U_SHIFT 24
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#define CFG_SC6 0x18
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#define CFG_ROW_ACC_INIT_RAV_MASK 0x03ff
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#define CFG_ROW_ACC_INIT_RAV_SHIFT 0
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#define CFG_ROW_ACC_INIT_RAV_B_MASK 0x03ff
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#define CFG_ROW_ACC_INIT_RAV_B_SHIFT 10
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#define CFG_SC8 0x20
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#define CFG_NLIN_LEFT_MASK 0x07ff
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#define CFG_NLIN_LEFT_SHIFT 0
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#define CFG_NLIN_RIGHT_MASK 0x07ff
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#define CFG_NLIN_RIGHT_SHIFT 12
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#define CFG_SC9 0x24
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#define CFG_LIN_ACC_INC CFG_SC9
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#define CFG_SC10 0x28
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#define CFG_NLIN_ACC_INIT CFG_SC10
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#define CFG_SC11 0x2c
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#define CFG_NLIN_ACC_INC CFG_SC11
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#define CFG_SC12 0x30
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#define CFG_COL_ACC_OFFSET_MASK 0x01ffffff
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#define CFG_COL_ACC_OFFSET_SHIFT 0
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#define CFG_SC13 0x34
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#define CFG_SC_FACTOR_RAV_MASK 0xff
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#define CFG_SC_FACTOR_RAV_SHIFT 0
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#define CFG_CHROMA_INTP_THR_MASK 0x03ff
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#define CFG_CHROMA_INTP_THR_SHIFT 12
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#define CFG_DELTA_CHROMA_THR_MASK 0x0f
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#define CFG_DELTA_CHROMA_THR_SHIFT 24
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#define CFG_SC17 0x44
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#define CFG_EV_THR_MASK 0x03ff
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#define CFG_EV_THR_SHIFT 12
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#define CFG_DELTA_LUMA_THR_MASK 0x0f
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#define CFG_DELTA_LUMA_THR_SHIFT 24
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#define CFG_DELTA_EV_THR_MASK 0x0f
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#define CFG_DELTA_EV_THR_SHIFT 28
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#define CFG_SC18 0x48
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#define CFG_HS_FACTOR_MASK 0x03ff
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#define CFG_HS_FACTOR_SHIFT 0
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#define CFG_CONF_DEFAULT_MASK 0x01ff
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#define CFG_CONF_DEFAULT_SHIFT 16
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#define CFG_SC19 0x4c
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#define CFG_HPF_COEFF0_MASK 0xff
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#define CFG_HPF_COEFF0_SHIFT 0
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#define CFG_HPF_COEFF1_MASK 0xff
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#define CFG_HPF_COEFF1_SHIFT 8
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#define CFG_HPF_COEFF2_MASK 0xff
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#define CFG_HPF_COEFF2_SHIFT 16
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#define CFG_HPF_COEFF3_MASK 0xff
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#define CFG_HPF_COEFF3_SHIFT 23
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#define CFG_SC20 0x50
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#define CFG_HPF_COEFF4_MASK 0xff
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#define CFG_HPF_COEFF4_SHIFT 0
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#define CFG_HPF_COEFF5_MASK 0xff
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#define CFG_HPF_COEFF5_SHIFT 8
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#define CFG_HPF_NORM_SHIFT_MASK 0x07
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#define CFG_HPF_NORM_SHIFT_SHIFT 16
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#define CFG_NL_LIMIT_MASK 0x1ff
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#define CFG_NL_LIMIT_SHIFT 20
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#define CFG_SC21 0x54
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#define CFG_NL_LO_THR_MASK 0x01ff
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#define CFG_NL_LO_THR_SHIFT 0
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#define CFG_NL_LO_SLOPE_MASK 0xff
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#define CFG_NL_LO_SLOPE_SHIFT 16
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#define CFG_SC22 0x58
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#define CFG_NL_HI_THR_MASK 0x01ff
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#define CFG_NL_HI_THR_SHIFT 0
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#define CFG_NL_HI_SLOPE_SH_MASK 0x07
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#define CFG_NL_HI_SLOPE_SH_SHIFT 16
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#define CFG_SC23 0x5c
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#define CFG_GRADIENT_THR_MASK 0x07ff
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#define CFG_GRADIENT_THR_SHIFT 0
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#define CFG_GRADIENT_THR_RANGE_MASK 0x0f
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#define CFG_GRADIENT_THR_RANGE_SHIFT 12
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#define CFG_MIN_GY_THR_MASK 0xff
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#define CFG_MIN_GY_THR_SHIFT 16
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#define CFG_MIN_GY_THR_RANGE_MASK 0x0f
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#define CFG_MIN_GY_THR_RANGE_SHIFT 28
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#define CFG_SC24 0x60
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#define CFG_ORG_H_MASK 0x07ff
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#define CFG_ORG_H_SHIFT 0
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#define CFG_ORG_W_MASK 0x07ff
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#define CFG_ORG_W_SHIFT 16
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#define CFG_SC25 0x64
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#define CFG_OFF_H_MASK 0x07ff
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#define CFG_OFF_H_SHIFT 0
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#define CFG_OFF_W_MASK 0x07ff
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#define CFG_OFF_W_SHIFT 16
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struct sc_data {
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void __iomem *base;
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struct resource *res;
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struct platform_device *pdev;
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};
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void sc_set_regs_bypass(struct sc_data *sc, u32 *sc_reg0);
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void sc_dump_regs(struct sc_data *sc);
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struct sc_data *sc_create(struct platform_device *pdev);
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#endif
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@ -43,6 +43,7 @@
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#include "vpdma.h"
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#include "vpe_regs.h"
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#include "sc.h"
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#define VPE_MODULE_NAME "vpe"
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@ -324,9 +325,11 @@ struct vpe_dev {
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int irq;
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void __iomem *base;
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struct resource *res;
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struct vb2_alloc_ctx *alloc_ctx;
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struct vpdma_data *vpdma; /* vpdma data handle */
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struct sc_data *sc; /* scaler data handle */
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};
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/*
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@ -443,6 +446,9 @@ struct vpe_mmr_adb {
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u32 csc_pad[2];
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};
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#define GET_OFFSET_TOP(ctx, obj, reg) \
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((obj)->res->start - ctx->dev->res->start + reg)
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#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
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VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
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/*
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@ -455,7 +461,8 @@ static void init_adb_hdrs(struct vpe_ctx *ctx)
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VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
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VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
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VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
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VPE_SET_MMR_ADB_HDR(ctx, sc_hdr, sc_regs, VPE_SC_MP_SC0);
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VPE_SET_MMR_ADB_HDR(ctx, sc_hdr, sc_regs,
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GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
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VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, VPE_CSC_CSC00);
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};
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@ -749,18 +756,6 @@ static void set_csc_coeff_bypass(struct vpe_ctx *ctx)
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ctx->load_mmrs = true;
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}
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static void set_sc_regs_bypass(struct vpe_ctx *ctx)
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{
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struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
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u32 *sc_reg0 = &mmr_adb->sc_regs[0];
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u32 val = 0;
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val |= VPE_SC_BYPASS;
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*sc_reg0 = val;
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ctx->load_mmrs = true;
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}
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/*
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* Set the shadow registers whose values are modified when either the
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* source or destination format is changed.
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@ -769,6 +764,7 @@ static int set_srcdst_params(struct vpe_ctx *ctx)
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{
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struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
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struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
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struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
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size_t mv_buf_size;
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int ret;
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@ -806,7 +802,7 @@ static int set_srcdst_params(struct vpe_ctx *ctx)
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set_cfg_and_line_modes(ctx);
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set_dei_regs(ctx);
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set_csc_coeff_bypass(ctx);
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set_sc_regs_bypass(ctx);
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sc_set_regs_bypass(ctx->dev->sc, &mmr_adb->sc_regs[0]);
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return 0;
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}
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@ -922,28 +918,6 @@ static void vpe_dump_regs(struct vpe_dev *dev)
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DUMPREG(DEI_FMD_STATUS_R0);
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DUMPREG(DEI_FMD_STATUS_R1);
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DUMPREG(DEI_FMD_STATUS_R2);
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DUMPREG(SC_MP_SC0);
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DUMPREG(SC_MP_SC1);
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DUMPREG(SC_MP_SC2);
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DUMPREG(SC_MP_SC3);
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DUMPREG(SC_MP_SC4);
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DUMPREG(SC_MP_SC5);
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DUMPREG(SC_MP_SC6);
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DUMPREG(SC_MP_SC8);
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DUMPREG(SC_MP_SC9);
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DUMPREG(SC_MP_SC10);
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DUMPREG(SC_MP_SC11);
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DUMPREG(SC_MP_SC12);
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DUMPREG(SC_MP_SC13);
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DUMPREG(SC_MP_SC17);
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DUMPREG(SC_MP_SC18);
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DUMPREG(SC_MP_SC19);
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DUMPREG(SC_MP_SC20);
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DUMPREG(SC_MP_SC21);
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DUMPREG(SC_MP_SC22);
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DUMPREG(SC_MP_SC23);
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DUMPREG(SC_MP_SC24);
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DUMPREG(SC_MP_SC25);
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DUMPREG(CSC_CSC00);
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DUMPREG(CSC_CSC01);
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DUMPREG(CSC_CSC02);
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@ -951,6 +925,8 @@ static void vpe_dump_regs(struct vpe_dev *dev)
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DUMPREG(CSC_CSC04);
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DUMPREG(CSC_CSC05);
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#undef DUMPREG
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sc_dump_regs(dev->sc);
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}
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static void add_out_dtd(struct vpe_ctx *ctx, int port)
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@ -1965,7 +1941,6 @@ static int vpe_probe(struct platform_device *pdev)
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{
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struct vpe_dev *dev;
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struct video_device *vfd;
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struct resource *res;
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int ret, irq, func;
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dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
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@ -1981,14 +1956,15 @@ static int vpe_probe(struct platform_device *pdev)
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atomic_set(&dev->num_instances, 0);
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mutex_init(&dev->dev_mutex);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpe_top");
|
||||
dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"vpe_top");
|
||||
/*
|
||||
* HACK: we get resource info from device tree in the form of a list of
|
||||
* VPE sub blocks, the driver currently uses only the base of vpe_top
|
||||
* for register access, the driver should be changed later to access
|
||||
* registers based on the sub block base addresses
|
||||
*/
|
||||
dev->base = devm_ioremap(&pdev->dev, res->start, SZ_32K);
|
||||
dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
|
||||
if (!dev->base) {
|
||||
ret = -ENOMEM;
|
||||
goto v4l2_dev_unreg;
|
||||
|
|
@ -2033,6 +2009,12 @@ static int vpe_probe(struct platform_device *pdev)
|
|||
|
||||
vpe_top_vpdma_reset(dev);
|
||||
|
||||
dev->sc = sc_create(pdev);
|
||||
if (IS_ERR(dev->sc)) {
|
||||
ret = PTR_ERR(dev->sc);
|
||||
goto runtime_put;
|
||||
}
|
||||
|
||||
dev->vpdma = vpdma_create(pdev);
|
||||
if (IS_ERR(dev->vpdma)) {
|
||||
ret = PTR_ERR(dev->vpdma);
|
||||
|
|
|
|||
|
|
@ -306,155 +306,6 @@
|
|||
#define VPE_FMD_FRAME_DIFF_MASK 0x000fffff
|
||||
#define VPE_FMD_FRAME_DIFF_SHIFT 0
|
||||
|
||||
/* VPE scaler regs */
|
||||
#define VPE_SC_MP_SC0 0x0700
|
||||
#define VPE_INTERLACE_O (1 << 0)
|
||||
#define VPE_LINEAR (1 << 1)
|
||||
#define VPE_SC_BYPASS (1 << 2)
|
||||
#define VPE_INVT_FID (1 << 3)
|
||||
#define VPE_USE_RAV (1 << 4)
|
||||
#define VPE_ENABLE_EV (1 << 5)
|
||||
#define VPE_AUTO_HS (1 << 6)
|
||||
#define VPE_DCM_2X (1 << 7)
|
||||
#define VPE_DCM_4X (1 << 8)
|
||||
#define VPE_HP_BYPASS (1 << 9)
|
||||
#define VPE_INTERLACE_I (1 << 10)
|
||||
#define VPE_ENABLE_SIN2_VER_INTP (1 << 11)
|
||||
#define VPE_Y_PK_EN (1 << 14)
|
||||
#define VPE_TRIM (1 << 15)
|
||||
#define VPE_SELFGEN_FID (1 << 16)
|
||||
|
||||
#define VPE_SC_MP_SC1 0x0704
|
||||
#define VPE_ROW_ACC_INC_MASK 0x07ffffff
|
||||
#define VPE_ROW_ACC_INC_SHIFT 0
|
||||
|
||||
#define VPE_SC_MP_SC2 0x0708
|
||||
#define VPE_ROW_ACC_OFFSET_MASK 0x0fffffff
|
||||
#define VPE_ROW_ACC_OFFSET_SHIFT 0
|
||||
|
||||
#define VPE_SC_MP_SC3 0x070c
|
||||
#define VPE_ROW_ACC_OFFSET_B_MASK 0x0fffffff
|
||||
#define VPE_ROW_ACC_OFFSET_B_SHIFT 0
|
||||
|
||||
#define VPE_SC_MP_SC4 0x0710
|
||||
#define VPE_TAR_H_MASK 0x07ff
|
||||
#define VPE_TAR_H_SHIFT 0
|
||||
#define VPE_TAR_W_MASK 0x07ff
|
||||
#define VPE_TAR_W_SHIFT 12
|
||||
#define VPE_LIN_ACC_INC_U_MASK 0x07
|
||||
#define VPE_LIN_ACC_INC_U_SHIFT 24
|
||||
#define VPE_NLIN_ACC_INIT_U_MASK 0x07
|
||||
#define VPE_NLIN_ACC_INIT_U_SHIFT 28
|
||||
|
||||
#define VPE_SC_MP_SC5 0x0714
|
||||
#define VPE_SRC_H_MASK 0x07ff
|
||||
#define VPE_SRC_H_SHIFT 0
|
||||
#define VPE_SRC_W_MASK 0x07ff
|
||||
#define VPE_SRC_W_SHIFT 12
|
||||
#define VPE_NLIN_ACC_INC_U_MASK 0x07
|
||||
#define VPE_NLIN_ACC_INC_U_SHIFT 24
|
||||
|
||||
#define VPE_SC_MP_SC6 0x0718
|
||||
#define VPE_ROW_ACC_INIT_RAV_MASK 0x03ff
|
||||
#define VPE_ROW_ACC_INIT_RAV_SHIFT 0
|
||||
#define VPE_ROW_ACC_INIT_RAV_B_MASK 0x03ff
|
||||
#define VPE_ROW_ACC_INIT_RAV_B_SHIFT 10
|
||||
|
||||
#define VPE_SC_MP_SC8 0x0720
|
||||
#define VPE_NLIN_LEFT_MASK 0x07ff
|
||||
#define VPE_NLIN_LEFT_SHIFT 0
|
||||
#define VPE_NLIN_RIGHT_MASK 0x07ff
|
||||
#define VPE_NLIN_RIGHT_SHIFT 12
|
||||
|
||||
#define VPE_SC_MP_SC9 0x0724
|
||||
#define VPE_LIN_ACC_INC VPE_SC_MP_SC9
|
||||
|
||||
#define VPE_SC_MP_SC10 0x0728
|
||||
#define VPE_NLIN_ACC_INIT VPE_SC_MP_SC10
|
||||
|
||||
#define VPE_SC_MP_SC11 0x072c
|
||||
#define VPE_NLIN_ACC_INC VPE_SC_MP_SC11
|
||||
|
||||
#define VPE_SC_MP_SC12 0x0730
|
||||
#define VPE_COL_ACC_OFFSET_MASK 0x01ffffff
|
||||
#define VPE_COL_ACC_OFFSET_SHIFT 0
|
||||
|
||||
#define VPE_SC_MP_SC13 0x0734
|
||||
#define VPE_SC_FACTOR_RAV_MASK 0x03ff
|
||||
#define VPE_SC_FACTOR_RAV_SHIFT 0
|
||||
#define VPE_CHROMA_INTP_THR_MASK 0x03ff
|
||||
#define VPE_CHROMA_INTP_THR_SHIFT 12
|
||||
#define VPE_DELTA_CHROMA_THR_MASK 0x0f
|
||||
#define VPE_DELTA_CHROMA_THR_SHIFT 24
|
||||
|
||||
#define VPE_SC_MP_SC17 0x0744
|
||||
#define VPE_EV_THR_MASK 0x03ff
|
||||
#define VPE_EV_THR_SHIFT 12
|
||||
#define VPE_DELTA_LUMA_THR_MASK 0x0f
|
||||
#define VPE_DELTA_LUMA_THR_SHIFT 24
|
||||
#define VPE_DELTA_EV_THR_MASK 0x0f
|
||||
#define VPE_DELTA_EV_THR_SHIFT 28
|
||||
|
||||
#define VPE_SC_MP_SC18 0x0748
|
||||
#define VPE_HS_FACTOR_MASK 0x03ff
|
||||
#define VPE_HS_FACTOR_SHIFT 0
|
||||
#define VPE_CONF_DEFAULT_MASK 0x01ff
|
||||
#define VPE_CONF_DEFAULT_SHIFT 16
|
||||
|
||||
#define VPE_SC_MP_SC19 0x074c
|
||||
#define VPE_HPF_COEFF0_MASK 0xff
|
||||
#define VPE_HPF_COEFF0_SHIFT 0
|
||||
#define VPE_HPF_COEFF1_MASK 0xff
|
||||
#define VPE_HPF_COEFF1_SHIFT 8
|
||||
#define VPE_HPF_COEFF2_MASK 0xff
|
||||
#define VPE_HPF_COEFF2_SHIFT 16
|
||||
#define VPE_HPF_COEFF3_MASK 0xff
|
||||
#define VPE_HPF_COEFF3_SHIFT 23
|
||||
|
||||
#define VPE_SC_MP_SC20 0x0750
|
||||
#define VPE_HPF_COEFF4_MASK 0xff
|
||||
#define VPE_HPF_COEFF4_SHIFT 0
|
||||
#define VPE_HPF_COEFF5_MASK 0xff
|
||||
#define VPE_HPF_COEFF5_SHIFT 8
|
||||
#define VPE_HPF_NORM_SHIFT_MASK 0x07
|
||||
#define VPE_HPF_NORM_SHIFT_SHIFT 16
|
||||
#define VPE_NL_LIMIT_MASK 0x1ff
|
||||
#define VPE_NL_LIMIT_SHIFT 20
|
||||
|
||||
#define VPE_SC_MP_SC21 0x0754
|
||||
#define VPE_NL_LO_THR_MASK 0x01ff
|
||||
#define VPE_NL_LO_THR_SHIFT 0
|
||||
#define VPE_NL_LO_SLOPE_MASK 0xff
|
||||
#define VPE_NL_LO_SLOPE_SHIFT 16
|
||||
|
||||
#define VPE_SC_MP_SC22 0x0758
|
||||
#define VPE_NL_HI_THR_MASK 0x01ff
|
||||
#define VPE_NL_HI_THR_SHIFT 0
|
||||
#define VPE_NL_HI_SLOPE_SH_MASK 0x07
|
||||
#define VPE_NL_HI_SLOPE_SH_SHIFT 16
|
||||
|
||||
#define VPE_SC_MP_SC23 0x075c
|
||||
#define VPE_GRADIENT_THR_MASK 0x07ff
|
||||
#define VPE_GRADIENT_THR_SHIFT 0
|
||||
#define VPE_GRADIENT_THR_RANGE_MASK 0x0f
|
||||
#define VPE_GRADIENT_THR_RANGE_SHIFT 12
|
||||
#define VPE_MIN_GY_THR_MASK 0xff
|
||||
#define VPE_MIN_GY_THR_SHIFT 16
|
||||
#define VPE_MIN_GY_THR_RANGE_MASK 0x0f
|
||||
#define VPE_MIN_GY_THR_RANGE_SHIFT 28
|
||||
|
||||
#define VPE_SC_MP_SC24 0x0760
|
||||
#define VPE_ORG_H_MASK 0x07ff
|
||||
#define VPE_ORG_H_SHIFT 0
|
||||
#define VPE_ORG_W_MASK 0x07ff
|
||||
#define VPE_ORG_W_SHIFT 16
|
||||
|
||||
#define VPE_SC_MP_SC25 0x0764
|
||||
#define VPE_OFF_H_MASK 0x07ff
|
||||
#define VPE_OFF_H_SHIFT 0
|
||||
#define VPE_OFF_W_MASK 0x07ff
|
||||
#define VPE_OFF_W_SHIFT 16
|
||||
|
||||
/* VPE color space converter regs */
|
||||
#define VPE_CSC_CSC00 0x5700
|
||||
#define VPE_CSC_A0_MASK 0x1fff
|
||||
|
|
|
|||
Loading…
Reference in New Issue