perf/x86: Move branch classifier
Commit 3e702ff6d1 ("perf/x86: Add LBR software filter support for Intel
CPUs") introduces a software branch filter which complements the hardware
branch filter and adds an x86 branch classifier.
Move the branch classifier to arch/x86/events/ so that it can be utilized
by other vendors for branch record filtering.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/bae5b95470d6bd49f40954bd379f414f5afcb965.1660211399.git.sandipan.das@amd.com
This commit is contained in:
Sandipan Das
Peter Zijlstra
parent
f4f925dae7
commit
4462fbfe6e
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y += core.o probe.o
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obj-y += core.o probe.o utils.o
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obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += rapl.o
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obj-y += amd/
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obj-$(CONFIG_X86_LOCAL_APIC) += msr.o
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@ -4,7 +4,6 @@
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#include <asm/perf_event.h>
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#include <asm/msr.h>
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#include <asm/insn.h>
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#include "../perf_event.h"
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@ -65,65 +64,6 @@
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#define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
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/*
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* x86control flow change classification
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* x86control flow changes include branches, interrupts, traps, faults
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*/
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enum {
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X86_BR_NONE = 0, /* unknown */
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X86_BR_USER = 1 << 0, /* branch target is user */
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X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
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X86_BR_CALL = 1 << 2, /* call */
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X86_BR_RET = 1 << 3, /* return */
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X86_BR_SYSCALL = 1 << 4, /* syscall */
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X86_BR_SYSRET = 1 << 5, /* syscall return */
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X86_BR_INT = 1 << 6, /* sw interrupt */
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X86_BR_IRET = 1 << 7, /* return from interrupt */
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X86_BR_JCC = 1 << 8, /* conditional */
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X86_BR_JMP = 1 << 9, /* jump */
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X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
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X86_BR_IND_CALL = 1 << 11,/* indirect calls */
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X86_BR_ABORT = 1 << 12,/* transaction abort */
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X86_BR_IN_TX = 1 << 13,/* in transaction */
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X86_BR_NO_TX = 1 << 14,/* not in transaction */
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X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
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X86_BR_CALL_STACK = 1 << 16,/* call stack */
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X86_BR_IND_JMP = 1 << 17,/* indirect jump */
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X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
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};
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#define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
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#define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
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#define X86_BR_ANY \
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(X86_BR_CALL |\
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X86_BR_RET |\
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X86_BR_SYSCALL |\
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X86_BR_SYSRET |\
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X86_BR_INT |\
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X86_BR_IRET |\
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X86_BR_JCC |\
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X86_BR_JMP |\
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X86_BR_IRQ |\
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X86_BR_ABORT |\
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X86_BR_IND_CALL |\
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X86_BR_IND_JMP |\
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X86_BR_ZERO_CALL)
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#define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
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#define X86_BR_ANY_CALL \
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(X86_BR_CALL |\
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X86_BR_IND_CALL |\
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X86_BR_ZERO_CALL |\
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X86_BR_SYSCALL |\
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X86_BR_IRQ |\
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X86_BR_INT)
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/*
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* Intel LBR_CTL bits
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*
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@ -1143,219 +1083,6 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
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return ret;
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}
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/*
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* return the type of control flow change at address "from"
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* instruction is not necessarily a branch (in case of interrupt).
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*
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* The branch type returned also includes the priv level of the
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* target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
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*
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* If a branch type is unknown OR the instruction cannot be
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* decoded (e.g., text page not present), then X86_BR_NONE is
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* returned.
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*/
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static int branch_type(unsigned long from, unsigned long to, int abort)
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{
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struct insn insn;
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void *addr;
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int bytes_read, bytes_left;
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int ret = X86_BR_NONE;
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int ext, to_plm, from_plm;
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u8 buf[MAX_INSN_SIZE];
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int is64 = 0;
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to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
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from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
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/*
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* maybe zero if lbr did not fill up after a reset by the time
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* we get a PMU interrupt
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*/
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if (from == 0 || to == 0)
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return X86_BR_NONE;
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if (abort)
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return X86_BR_ABORT | to_plm;
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if (from_plm == X86_BR_USER) {
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/*
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* can happen if measuring at the user level only
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* and we interrupt in a kernel thread, e.g., idle.
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*/
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if (!current->mm)
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return X86_BR_NONE;
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/* may fail if text not present */
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bytes_left = copy_from_user_nmi(buf, (void __user *)from,
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MAX_INSN_SIZE);
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bytes_read = MAX_INSN_SIZE - bytes_left;
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if (!bytes_read)
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return X86_BR_NONE;
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addr = buf;
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} else {
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/*
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* The LBR logs any address in the IP, even if the IP just
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* faulted. This means userspace can control the from address.
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* Ensure we don't blindly read any address by validating it is
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* a known text address.
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*/
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if (kernel_text_address(from)) {
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addr = (void *)from;
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/*
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* Assume we can get the maximum possible size
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* when grabbing kernel data. This is not
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* _strictly_ true since we could possibly be
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* executing up next to a memory hole, but
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* it is very unlikely to be a problem.
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*/
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bytes_read = MAX_INSN_SIZE;
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} else {
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return X86_BR_NONE;
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}
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}
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/*
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* decoder needs to know the ABI especially
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* on 64-bit systems running 32-bit apps
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*/
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#ifdef CONFIG_X86_64
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is64 = kernel_ip((unsigned long)addr) || any_64bit_mode(current_pt_regs());
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#endif
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insn_init(&insn, addr, bytes_read, is64);
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if (insn_get_opcode(&insn))
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return X86_BR_ABORT;
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switch (insn.opcode.bytes[0]) {
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case 0xf:
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switch (insn.opcode.bytes[1]) {
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case 0x05: /* syscall */
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case 0x34: /* sysenter */
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ret = X86_BR_SYSCALL;
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break;
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case 0x07: /* sysret */
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case 0x35: /* sysexit */
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ret = X86_BR_SYSRET;
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break;
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case 0x80 ... 0x8f: /* conditional */
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ret = X86_BR_JCC;
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break;
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default:
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ret = X86_BR_NONE;
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}
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break;
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case 0x70 ... 0x7f: /* conditional */
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ret = X86_BR_JCC;
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break;
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case 0xc2: /* near ret */
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case 0xc3: /* near ret */
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case 0xca: /* far ret */
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case 0xcb: /* far ret */
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ret = X86_BR_RET;
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break;
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case 0xcf: /* iret */
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ret = X86_BR_IRET;
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break;
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case 0xcc ... 0xce: /* int */
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ret = X86_BR_INT;
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break;
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case 0xe8: /* call near rel */
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if (insn_get_immediate(&insn) || insn.immediate1.value == 0) {
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/* zero length call */
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ret = X86_BR_ZERO_CALL;
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break;
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}
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fallthrough;
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case 0x9a: /* call far absolute */
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ret = X86_BR_CALL;
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break;
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case 0xe0 ... 0xe3: /* loop jmp */
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ret = X86_BR_JCC;
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break;
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case 0xe9 ... 0xeb: /* jmp */
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ret = X86_BR_JMP;
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break;
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case 0xff: /* call near absolute, call far absolute ind */
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if (insn_get_modrm(&insn))
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return X86_BR_ABORT;
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ext = (insn.modrm.bytes[0] >> 3) & 0x7;
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switch (ext) {
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case 2: /* near ind call */
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case 3: /* far ind call */
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ret = X86_BR_IND_CALL;
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break;
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case 4:
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case 5:
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ret = X86_BR_IND_JMP;
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break;
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}
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break;
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default:
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ret = X86_BR_NONE;
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}
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/*
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* interrupts, traps, faults (and thus ring transition) may
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* occur on any instructions. Thus, to classify them correctly,
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* we need to first look at the from and to priv levels. If they
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* are different and to is in the kernel, then it indicates
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* a ring transition. If the from instruction is not a ring
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* transition instr (syscall, systenter, int), then it means
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* it was a irq, trap or fault.
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*
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* we have no way of detecting kernel to kernel faults.
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*/
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if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
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&& ret != X86_BR_SYSCALL && ret != X86_BR_INT)
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ret = X86_BR_IRQ;
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/*
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* branch priv level determined by target as
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* is done by HW when LBR_SELECT is implemented
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*/
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if (ret != X86_BR_NONE)
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ret |= to_plm;
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return ret;
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}
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#define X86_BR_TYPE_MAP_MAX 16
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static int branch_map[X86_BR_TYPE_MAP_MAX] = {
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PERF_BR_CALL, /* X86_BR_CALL */
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PERF_BR_RET, /* X86_BR_RET */
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PERF_BR_SYSCALL, /* X86_BR_SYSCALL */
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PERF_BR_SYSRET, /* X86_BR_SYSRET */
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PERF_BR_UNKNOWN, /* X86_BR_INT */
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PERF_BR_ERET, /* X86_BR_IRET */
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PERF_BR_COND, /* X86_BR_JCC */
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PERF_BR_UNCOND, /* X86_BR_JMP */
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PERF_BR_IRQ, /* X86_BR_IRQ */
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PERF_BR_IND_CALL, /* X86_BR_IND_CALL */
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PERF_BR_UNKNOWN, /* X86_BR_ABORT */
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PERF_BR_UNKNOWN, /* X86_BR_IN_TX */
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PERF_BR_UNKNOWN, /* X86_BR_NO_TX */
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PERF_BR_CALL, /* X86_BR_ZERO_CALL */
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PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */
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PERF_BR_IND, /* X86_BR_IND_JMP */
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};
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static int
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common_branch_type(int type)
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{
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int i;
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type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */
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if (type) {
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i = __ffs(type);
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if (i < X86_BR_TYPE_MAP_MAX)
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return branch_map[i];
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}
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return PERF_BR_UNKNOWN;
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}
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enum {
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ARCH_LBR_BR_TYPE_JCC = 0,
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ARCH_LBR_BR_TYPE_NEAR_IND_JMP = 1,
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@ -1210,6 +1210,68 @@ static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
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regs->ip = ip;
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}
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/*
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* x86control flow change classification
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* x86control flow changes include branches, interrupts, traps, faults
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*/
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enum {
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X86_BR_NONE = 0, /* unknown */
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X86_BR_USER = 1 << 0, /* branch target is user */
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X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
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X86_BR_CALL = 1 << 2, /* call */
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X86_BR_RET = 1 << 3, /* return */
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X86_BR_SYSCALL = 1 << 4, /* syscall */
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X86_BR_SYSRET = 1 << 5, /* syscall return */
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X86_BR_INT = 1 << 6, /* sw interrupt */
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X86_BR_IRET = 1 << 7, /* return from interrupt */
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X86_BR_JCC = 1 << 8, /* conditional */
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X86_BR_JMP = 1 << 9, /* jump */
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X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
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X86_BR_IND_CALL = 1 << 11,/* indirect calls */
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X86_BR_ABORT = 1 << 12,/* transaction abort */
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X86_BR_IN_TX = 1 << 13,/* in transaction */
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X86_BR_NO_TX = 1 << 14,/* not in transaction */
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X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
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X86_BR_CALL_STACK = 1 << 16,/* call stack */
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X86_BR_IND_JMP = 1 << 17,/* indirect jump */
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X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
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};
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#define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
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#define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
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#define X86_BR_ANY \
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(X86_BR_CALL |\
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X86_BR_RET |\
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X86_BR_SYSCALL |\
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X86_BR_SYSRET |\
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X86_BR_INT |\
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X86_BR_IRET |\
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X86_BR_JCC |\
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X86_BR_JMP |\
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X86_BR_IRQ |\
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X86_BR_ABORT |\
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X86_BR_IND_CALL |\
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X86_BR_IND_JMP |\
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X86_BR_ZERO_CALL)
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#define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
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#define X86_BR_ANY_CALL \
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(X86_BR_CALL |\
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X86_BR_IND_CALL |\
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X86_BR_ZERO_CALL |\
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X86_BR_SYSCALL |\
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X86_BR_IRQ |\
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X86_BR_INT)
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int common_branch_type(int type);
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int branch_type(unsigned long from, unsigned long to, int abort);
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ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
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ssize_t intel_event_sysfs_show(char *page, u64 config);
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@ -0,0 +1,216 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <asm/insn.h>
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#include "perf_event.h"
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/*
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* return the type of control flow change at address "from"
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* instruction is not necessarily a branch (in case of interrupt).
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*
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* The branch type returned also includes the priv level of the
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* target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
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*
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* If a branch type is unknown OR the instruction cannot be
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* decoded (e.g., text page not present), then X86_BR_NONE is
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* returned.
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*/
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int branch_type(unsigned long from, unsigned long to, int abort)
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{
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struct insn insn;
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void *addr;
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int bytes_read, bytes_left;
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int ret = X86_BR_NONE;
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int ext, to_plm, from_plm;
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u8 buf[MAX_INSN_SIZE];
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int is64 = 0;
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to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
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from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
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/*
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* maybe zero if lbr did not fill up after a reset by the time
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* we get a PMU interrupt
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*/
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if (from == 0 || to == 0)
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return X86_BR_NONE;
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if (abort)
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return X86_BR_ABORT | to_plm;
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if (from_plm == X86_BR_USER) {
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/*
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* can happen if measuring at the user level only
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* and we interrupt in a kernel thread, e.g., idle.
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*/
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if (!current->mm)
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return X86_BR_NONE;
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/* may fail if text not present */
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bytes_left = copy_from_user_nmi(buf, (void __user *)from,
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MAX_INSN_SIZE);
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bytes_read = MAX_INSN_SIZE - bytes_left;
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if (!bytes_read)
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return X86_BR_NONE;
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addr = buf;
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} else {
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/*
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* The LBR logs any address in the IP, even if the IP just
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* faulted. This means userspace can control the from address.
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* Ensure we don't blindly read any address by validating it is
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* a known text address.
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*/
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if (kernel_text_address(from)) {
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addr = (void *)from;
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/*
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* Assume we can get the maximum possible size
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* when grabbing kernel data. This is not
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* _strictly_ true since we could possibly be
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* executing up next to a memory hole, but
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* it is very unlikely to be a problem.
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*/
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bytes_read = MAX_INSN_SIZE;
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} else {
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return X86_BR_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* decoder needs to know the ABI especially
|
||||
* on 64-bit systems running 32-bit apps
|
||||
*/
|
||||
#ifdef CONFIG_X86_64
|
||||
is64 = kernel_ip((unsigned long)addr) || any_64bit_mode(current_pt_regs());
|
||||
#endif
|
||||
insn_init(&insn, addr, bytes_read, is64);
|
||||
if (insn_get_opcode(&insn))
|
||||
return X86_BR_ABORT;
|
||||
|
||||
switch (insn.opcode.bytes[0]) {
|
||||
case 0xf:
|
||||
switch (insn.opcode.bytes[1]) {
|
||||
case 0x05: /* syscall */
|
||||
case 0x34: /* sysenter */
|
||||
ret = X86_BR_SYSCALL;
|
||||
break;
|
||||
case 0x07: /* sysret */
|
||||
case 0x35: /* sysexit */
|
||||
ret = X86_BR_SYSRET;
|
||||
break;
|
||||
case 0x80 ... 0x8f: /* conditional */
|
||||
ret = X86_BR_JCC;
|
||||
break;
|
||||
default:
|
||||
ret = X86_BR_NONE;
|
||||
}
|
||||
break;
|
||||
case 0x70 ... 0x7f: /* conditional */
|
||||
ret = X86_BR_JCC;
|
||||
break;
|
||||
case 0xc2: /* near ret */
|
||||
case 0xc3: /* near ret */
|
||||
case 0xca: /* far ret */
|
||||
case 0xcb: /* far ret */
|
||||
ret = X86_BR_RET;
|
||||
break;
|
||||
case 0xcf: /* iret */
|
||||
ret = X86_BR_IRET;
|
||||
break;
|
||||
case 0xcc ... 0xce: /* int */
|
||||
ret = X86_BR_INT;
|
||||
break;
|
||||
case 0xe8: /* call near rel */
|
||||
if (insn_get_immediate(&insn) || insn.immediate1.value == 0) {
|
||||
/* zero length call */
|
||||
ret = X86_BR_ZERO_CALL;
|
||||
break;
|
||||
}
|
||||
fallthrough;
|
||||
case 0x9a: /* call far absolute */
|
||||
ret = X86_BR_CALL;
|
||||
break;
|
||||
case 0xe0 ... 0xe3: /* loop jmp */
|
||||
ret = X86_BR_JCC;
|
||||
break;
|
||||
case 0xe9 ... 0xeb: /* jmp */
|
||||
ret = X86_BR_JMP;
|
||||
break;
|
||||
case 0xff: /* call near absolute, call far absolute ind */
|
||||
if (insn_get_modrm(&insn))
|
||||
return X86_BR_ABORT;
|
||||
|
||||
ext = (insn.modrm.bytes[0] >> 3) & 0x7;
|
||||
switch (ext) {
|
||||
case 2: /* near ind call */
|
||||
case 3: /* far ind call */
|
||||
ret = X86_BR_IND_CALL;
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
ret = X86_BR_IND_JMP;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ret = X86_BR_NONE;
|
||||
}
|
||||
/*
|
||||
* interrupts, traps, faults (and thus ring transition) may
|
||||
* occur on any instructions. Thus, to classify them correctly,
|
||||
* we need to first look at the from and to priv levels. If they
|
||||
* are different and to is in the kernel, then it indicates
|
||||
* a ring transition. If the from instruction is not a ring
|
||||
* transition instr (syscall, systenter, int), then it means
|
||||
* it was a irq, trap or fault.
|
||||
*
|
||||
* we have no way of detecting kernel to kernel faults.
|
||||
*/
|
||||
if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
|
||||
&& ret != X86_BR_SYSCALL && ret != X86_BR_INT)
|
||||
ret = X86_BR_IRQ;
|
||||
|
||||
/*
|
||||
* branch priv level determined by target as
|
||||
* is done by HW when LBR_SELECT is implemented
|
||||
*/
|
||||
if (ret != X86_BR_NONE)
|
||||
ret |= to_plm;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define X86_BR_TYPE_MAP_MAX 16
|
||||
|
||||
static int branch_map[X86_BR_TYPE_MAP_MAX] = {
|
||||
PERF_BR_CALL, /* X86_BR_CALL */
|
||||
PERF_BR_RET, /* X86_BR_RET */
|
||||
PERF_BR_SYSCALL, /* X86_BR_SYSCALL */
|
||||
PERF_BR_SYSRET, /* X86_BR_SYSRET */
|
||||
PERF_BR_UNKNOWN, /* X86_BR_INT */
|
||||
PERF_BR_ERET, /* X86_BR_IRET */
|
||||
PERF_BR_COND, /* X86_BR_JCC */
|
||||
PERF_BR_UNCOND, /* X86_BR_JMP */
|
||||
PERF_BR_IRQ, /* X86_BR_IRQ */
|
||||
PERF_BR_IND_CALL, /* X86_BR_IND_CALL */
|
||||
PERF_BR_UNKNOWN, /* X86_BR_ABORT */
|
||||
PERF_BR_UNKNOWN, /* X86_BR_IN_TX */
|
||||
PERF_BR_UNKNOWN, /* X86_BR_NO_TX */
|
||||
PERF_BR_CALL, /* X86_BR_ZERO_CALL */
|
||||
PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */
|
||||
PERF_BR_IND, /* X86_BR_IND_JMP */
|
||||
};
|
||||
|
||||
int common_branch_type(int type)
|
||||
{
|
||||
int i;
|
||||
|
||||
type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */
|
||||
|
||||
if (type) {
|
||||
i = __ffs(type);
|
||||
if (i < X86_BR_TYPE_MAP_MAX)
|
||||
return branch_map[i];
|
||||
}
|
||||
|
||||
return PERF_BR_UNKNOWN;
|
||||
}
|
||||
Loading…
Reference in New Issue