wl12xx: use frequency instead of enumerations for pdata clocks
Instead of defining an enumeration with the FW specific values for the different clock rates, use the actual frequency instead. Also add a boolean to specify whether the clock is XTAL or not. Change all board files to reflect this. Signed-off-by: Luciano Coelho <luca@coelho.fi> [Eliad - small fixes, update board file changes] Signed-off-by: Eliad Peller <eliad@wizery.com> Tested-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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6f921fab58
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44486b48b0
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@ -1386,7 +1386,8 @@ static const short da850_wl12xx_pins[] __initconst = {
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static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = {
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.irq = -1,
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.irq_trigger = IRQ_TYPE_EDGE_RISING,
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.board_ref_clock = WL12XX_REFCLOCK_38,
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.ref_clock_freq = 38400000,
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.ref_clock_xtal = false,
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};
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static __init int da850_wl12xx_init(void)
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@ -39,14 +39,14 @@ static struct twl4030_gpio_platform_data twl_gpio_auxdata;
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static struct wl12xx_platform_data wl12xx __initdata;
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static void __init __used legacy_init_wl12xx(unsigned ref_clock,
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unsigned tcxo_clock,
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static void __init __used legacy_init_wl12xx(u32 ref_clock_freq,
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u32 tcxo_clock_freq,
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int gpio)
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{
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int res;
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wl12xx.board_ref_clock = ref_clock;
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wl12xx.board_tcxo_clock = tcxo_clock;
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wl12xx.ref_clock_freq = ref_clock_freq;
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wl12xx.tcxo_clock_freq = tcxo_clock_freq;
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wl12xx.irq = gpio_to_irq(gpio);
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wl12xx.irq_trigger = IRQ_TYPE_LEVEL_HIGH;
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@ -57,8 +57,8 @@ static void __init __used legacy_init_wl12xx(unsigned ref_clock,
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}
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}
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#else
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static inline void legacy_init_wl12xx(unsigned ref_clock,
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unsigned tcxo_clock,
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static inline void legacy_init_wl12xx(u32 ref_clock_freq,
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u32 tcxo_clock_freq,
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int gpio)
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{
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}
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@ -130,7 +130,7 @@ static void __init omap3_sbc_t3730_twl_init(void)
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static void __init omap3_sbc_t3730_legacy_init(void)
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{
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omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
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legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
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legacy_init_wl12xx(38400000, 0, 136);
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}
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static void __init omap3_sbc_t3530_legacy_init(void)
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@ -175,12 +175,12 @@ static void __init omap3_igep0030_rev_g_legacy_init(void)
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static void __init omap3_evm_legacy_init(void)
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{
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hsmmc2_internal_input_clk();
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legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
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legacy_init_wl12xx(38400000, 0, 149);
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}
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static void __init omap3_zoom_legacy_init(void)
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{
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legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
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legacy_init_wl12xx(26000000, 0, 162);
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}
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static void am35xx_enable_emac_int(void)
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@ -247,7 +247,7 @@ static void __init omap3_sbc_t3517_legacy_init(void)
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am35xx_emac_reset();
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hsmmc2_internal_input_clk();
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omap3_sbc_t3517_wifi_init();
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legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145);
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legacy_init_wl12xx(38400000, 0, 145);
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}
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static void __init am3517_evm_legacy_init(void)
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@ -292,18 +292,17 @@ static void __init omap3_tao3530_legacy_init(void)
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#ifdef CONFIG_ARCH_OMAP4
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static void __init omap4_sdp_legacy_init(void)
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{
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legacy_init_wl12xx(WL12XX_REFCLOCK_26,
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WL12XX_TCXOCLOCK_26, 53);
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legacy_init_wl12xx(26000000, 26000000, 53);
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}
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static void __init omap4_panda_legacy_init(void)
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{
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legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
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legacy_init_wl12xx(38400000, 0, 53);
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}
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static void __init var_som_om44_legacy_init(void)
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{
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legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 41);
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legacy_init_wl12xx(38400000, 0, 41);
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}
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#endif
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@ -318,7 +317,7 @@ static struct iommu_platform_data omap4_iommu_pdata = {
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#ifdef CONFIG_SOC_AM33XX
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static void __init am335x_evmsk_legacy_init(void)
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{
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legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 31);
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legacy_init_wl12xx(38400000, 0, 31);
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}
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#endif
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@ -1770,6 +1770,40 @@ wl12xx_iface_combinations[] = {
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},
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};
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static const struct wl12xx_clock wl12xx_refclock_table[] = {
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{ 19200000, false, WL12XX_REFCLOCK_19 },
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{ 26000000, false, WL12XX_REFCLOCK_26 },
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{ 26000000, true, WL12XX_REFCLOCK_26_XTAL },
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{ 38400000, false, WL12XX_REFCLOCK_38 },
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{ 38400000, true, WL12XX_REFCLOCK_38_XTAL },
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{ 52000000, false, WL12XX_REFCLOCK_52 },
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{ 0, false, 0 }
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};
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static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
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{ 16368000, true, WL12XX_TCXOCLOCK_16_368 },
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{ 16800000, true, WL12XX_TCXOCLOCK_16_8 },
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{ 19200000, true, WL12XX_TCXOCLOCK_19_2 },
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{ 26000000, true, WL12XX_TCXOCLOCK_26 },
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{ 32736000, true, WL12XX_TCXOCLOCK_32_736 },
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{ 33600000, true, WL12XX_TCXOCLOCK_33_6 },
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{ 38400000, true, WL12XX_TCXOCLOCK_38_4 },
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{ 52000000, true, WL12XX_TCXOCLOCK_52 },
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{ 0, false, 0 }
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};
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static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
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u32 freq, bool xtal)
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{
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int i;
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for (i = 0; table[i].freq != 0; i++)
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if ((table[i].freq == freq) && (table[i].xtal == xtal))
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return table[i].hw_idx;
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return -EINVAL;
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}
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static int wl12xx_setup(struct wl1271 *wl)
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{
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struct wl12xx_priv *priv = wl->priv;
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@ -1799,7 +1833,17 @@ static int wl12xx_setup(struct wl1271 *wl)
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wl12xx_conf_init(wl);
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if (!fref_param) {
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priv->ref_clock = pdata->board_ref_clock;
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priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
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pdata->ref_clock_freq,
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pdata->ref_clock_xtal);
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if (priv->ref_clock < 0) {
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wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
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pdata->ref_clock_freq,
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pdata->ref_clock_xtal ?
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"XTAL" : "not XTAL");
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return priv->ref_clock;
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}
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} else {
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if (!strcmp(fref_param, "19.2"))
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priv->ref_clock = WL12XX_REFCLOCK_19;
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@ -1817,9 +1861,17 @@ static int wl12xx_setup(struct wl1271 *wl)
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wl1271_error("Invalid fref parameter %s", fref_param);
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}
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if (!tcxo_param) {
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priv->tcxo_clock = pdata->board_tcxo_clock;
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} else {
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if (!tcxo_param && pdata->tcxo_clock_freq) {
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priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
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pdata->tcxo_clock_freq,
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true);
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if (priv->tcxo_clock < 0) {
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wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
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pdata->tcxo_clock_freq);
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return priv->tcxo_clock;
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}
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} else if (tcxo_param) {
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if (!strcmp(tcxo_param, "19.2"))
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priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
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else if (!strcmp(tcxo_param, "26"))
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@ -82,6 +82,34 @@ struct wl12xx_priv {
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struct wl127x_rx_mem_pool_addr *rx_mem_addr;
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};
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/* Reference clock values */
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enum {
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WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
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WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
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WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
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WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
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WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
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WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
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};
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/* TCXO clock values */
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enum {
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WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
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WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
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WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
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WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
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WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */
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WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */
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WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */
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WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */
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};
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struct wl12xx_clock {
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u32 freq;
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bool xtal;
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u8 hw_idx;
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};
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struct wl12xx_fw_packet_counters {
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/* Cumulative counter of released packets per AC */
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u8 tx_released_pkts[NUM_TX_QUEUES];
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@ -26,28 +26,6 @@
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#include <linux/err.h>
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/* Reference clock values */
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enum {
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WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
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WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
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WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
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WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
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WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
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WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
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};
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/* TCXO clock values */
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enum {
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WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
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WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
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WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
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WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
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WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */
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WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */
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WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */
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WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */
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};
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struct wl1251_platform_data {
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int power_gpio;
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/* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */
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struct wl12xx_platform_data {
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int irq;
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u32 irq_trigger;
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int board_ref_clock;
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int board_tcxo_clock;
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bool ref_clock_xtal; /* specify whether the clock is XTAL or not */
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u32 ref_clock_freq; /* in Hertz */
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u32 tcxo_clock_freq; /* in Hertz, tcxo is always XTAL */
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bool pwr_in_suspend;
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};
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