arm/tegra: implement support for tegra30
Add support for tegra30 SoC. This includes a device tree compatible type for
this SoC ("nvidia,tegra30") and adds L2 cache initialization for this new SoC.
The clock framework is still missing, which prevents most drivers from working.
The basic IRQs are the same, so remove the dependency on
CONFIG_ARCH_TEGRA_2x_SOC.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Peter De Schrijver
Olof Johansson
parent
241682c8e0
commit
44107d8b7e
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@ -2,11 +2,8 @@ if ARCH_TEGRA
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comment "NVIDIA Tegra options"
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choice
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prompt "Select Tegra processor family for target system"
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config ARCH_TEGRA_2x_SOC
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bool "Tegra 2 family"
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bool "Enable support for Tegra20 family"
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select CPU_V7
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select ARM_GIC
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select ARCH_REQUIRE_GPIOLIB
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@ -17,7 +14,18 @@ config ARCH_TEGRA_2x_SOC
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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endchoice
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config ARCH_TEGRA_3x_SOC
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bool "Enable support for Tegra30 family"
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select CPU_V7
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select ARM_GIC
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select ARCH_REQUIRE_GPIOLIB
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select USB_ARCH_HAS_EHCI if USB_SUPPORT
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select USB_ULPI if USB_SUPPORT
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select USB_ULPI_VIEWPORT if USB_SUPPORT
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select USE_OF
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help
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Support for NVIDIA Tegra T30 processor family, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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config TEGRA_PCI
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bool "PCI Express support"
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@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
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obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
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@ -0,0 +1,62 @@
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/*
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* arch/arm/mach-tegra/board-dt-tegra30.c
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*
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* NVIDIA Tegra30 device tree board support
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*
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* Copyright (C) 2011 NVIDIA Corporation
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*
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* Derived from:
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*
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* arch/arm/mach-tegra/board-dt-tegra20.c
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*
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* Copyright (C) 2010 Secret Lab Technologies, Ltd.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include "board.h"
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static struct of_device_id tegra_dt_match_table[] __initdata = {
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{ .compatible = "simple-bus", },
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{}
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};
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static void __init tegra30_dt_init(void)
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{
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of_platform_populate(NULL, tegra_dt_match_table,
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NULL, NULL);
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}
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static const char *tegra30_dt_board_compat[] = {
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NULL
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};
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DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
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.map_io = tegra_map_common_io,
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.init_early = tegra30_init_early,
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.init_irq = tegra_dt_init_irq,
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.handle_irq = gic_handle_irq,
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.timer = &tegra_timer,
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.init_machine = tegra30_dt_init,
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.restart = tegra_assert_system_reset,
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.dt_compat = tegra30_dt_board_compat,
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MACHINE_END
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@ -26,6 +26,7 @@
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void tegra_assert_system_reset(char mode, const char *cmd);
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void __init tegra20_init_early(void);
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void __init tegra30_init_early(void);
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void __init tegra_map_common_io(void);
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void __init tegra_init_irq(void);
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void __init tegra_dt_init_irq(void);
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@ -102,3 +102,9 @@ void __init tegra20_init_early(void)
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tegra_init_cache(0x331, 0x441);
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}
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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void __init tegra30_init_early(void)
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{
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tegra_init_cache(0x441, 0x551);
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}
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#endif
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@ -25,7 +25,6 @@
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#define IRQ_LOCALTIMER 29
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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/* Primary Interrupt Controller */
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#define INT_PRI_BASE (INT_GIC_BASE + 32)
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#define INT_TMR1 (INT_PRI_BASE + 0)
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@ -178,6 +177,5 @@
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#define NR_BOARD_IRQS 32
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#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
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#endif
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#endif
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