RTC driver support for Phytium desktop and embedded CPUs
RTC driver function fix patch Support Phytium desktop and embedded processors, such as D2000 and E2000
Reviewed-by: Wang Nan <wangnan1505@phytium.com.cn>
(cherry picked from commit 00f079b210)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This commit is contained in:
Wang Nan
Jianping Liu
parent
9cd366d0b7
commit
43dd0e35f4
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@ -1897,6 +1897,16 @@ config RTC_DRV_ASPEED
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This driver can also be built as a module, if so, the module
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will be called "rtc-aspeed".
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config RTC_DRV_PHYTIUM
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tristate "Phytium RTC"
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depends on ARCH_PHYTIUM
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default y if ARCH_PHYTIUM
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help
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Say yes here to support the Phytium SoC real time clock.
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This driver can also be built as a module, if so, the module
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will be called "rtc-phytium".
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comment "HID Sensor RTC drivers"
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config RTC_DRV_HID_SENSOR_TIME
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@ -127,6 +127,7 @@ obj-$(CONFIG_RTC_DRV_PCF8523) += rtc-pcf8523.o
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obj-$(CONFIG_RTC_DRV_PCF85363) += rtc-pcf85363.o
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obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o
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obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o
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obj-$(CONFIG_RTC_DRV_PHYTIUM) += rtc-phytium.o
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obj-$(CONFIG_RTC_DRV_PIC32) += rtc-pic32.o
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obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o
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obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
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@ -0,0 +1,331 @@
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/*
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* Phytium Real Time Clock Driver
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*
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* Copyright (c) 2019, Phytium Technology Co., Ltd.
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*
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* Chen Baozi <chenbaozi@phytium.com.cn>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/rtc.h>
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#include <linux/acpi.h>
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#define RTC_CMR 0x04
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#define RTC_AES_SEL 0x08
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#define RTC_AES_SEL_COUNTER 0x100
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#define RTC_CCR 0x0C
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#define RTC_CCR_IE BIT(0)
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#define RTC_CCR_MASK BIT(1)
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#define RTC_CCR_EN BIT(2)
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#define RTC_CCR_WEN BIT(3)
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#define RTC_STAT 0x10
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#define RTC_STAT_BIT BIT(0)
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#define RTC_RSTAT 0x14
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#define RTC_EOI 0x18
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#define RTC_VER 0x1C
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#define RTC_CDR_LOW 0x20
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#define RTC_CCVR 0x24
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#define RTC_CLR_LOW 0x28
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#define RTC_CLR 0x2c
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#define RTC_COUNTER_HB_OFFSET 15
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#define RTC_COUNTER_LB_MASK 0x7fff
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spinlock_t spinlock_phytium_rtc;
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struct phytium_rtc_dev {
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struct rtc_device *rtc;
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struct device *dev;
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unsigned long alarm_time;
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void __iomem *csr_base;
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struct clk *clk;
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unsigned int irq_wake;
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unsigned int irq_enabled;
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};
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static int phytium_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct phytium_rtc_dev *pdata = dev_get_drvdata(dev);
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unsigned long counter = 0;
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unsigned long tmp = 0;
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spin_lock(&spinlock_phytium_rtc);
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writel(RTC_AES_SEL_COUNTER, pdata->csr_base + RTC_AES_SEL);
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counter = readl(pdata->csr_base + RTC_CCVR);
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tmp = readl(pdata->csr_base + RTC_CDR_LOW);
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printk("%s_%d:counter:0x%lx\n", __func__, __LINE__, counter);
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spin_unlock(&spinlock_phytium_rtc);
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rtc_time_to_tm(counter, tm);
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return rtc_valid_tm(tm);
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}
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static int phytium_rtc_set_mmss(struct device *dev, unsigned long secs)
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{
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struct phytium_rtc_dev *pdata = dev_get_drvdata(dev);
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unsigned long counter = 0;
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unsigned long tmp = 0;
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spin_lock(&spinlock_phytium_rtc);
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writel(RTC_AES_SEL_COUNTER, pdata->csr_base + RTC_AES_SEL);
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writel(0x00000000, pdata->csr_base + RTC_CLR_LOW);
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writel((u32)secs, pdata->csr_base + RTC_CLR);
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writel(RTC_AES_SEL_COUNTER, pdata->csr_base + RTC_AES_SEL);
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counter = readl(pdata->csr_base + RTC_CLR);
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tmp = readl(pdata->csr_base + RTC_CLR_LOW);
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spin_unlock(&spinlock_phytium_rtc);
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return 0;
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}
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static int phytium_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct phytium_rtc_dev *pdata = dev_get_drvdata(dev);
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rtc_time_to_tm(pdata->alarm_time, &alrm->time);
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alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
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return 0;
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}
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static int phytium_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
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{
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struct phytium_rtc_dev *pdata = dev_get_drvdata(dev);
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u32 ccr;
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ccr = readl(pdata->csr_base + RTC_CCR);
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if (enabled) {
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ccr &= ~RTC_CCR_MASK;
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ccr |= RTC_CCR_IE;
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} else {
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ccr &= ~RTC_CCR_IE;
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ccr |= RTC_CCR_MASK;
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}
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writel(ccr, pdata->csr_base + RTC_CCR);
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return 0;
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}
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static int phytium_rtc_alarm_irq_enabled(struct device *dev)
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{
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struct phytium_rtc_dev *pdata = dev_get_drvdata(dev);
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return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1: 0;
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}
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static int phytium_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct phytium_rtc_dev *pdata = dev_get_drvdata(dev);
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unsigned long rtc_time;
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unsigned long alarm_time;
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rtc_time = readl(pdata->csr_base + RTC_CCVR);
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rtc_tm_to_time(&alrm->time, &alarm_time);
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pdata->alarm_time = alarm_time;
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writel((u32) pdata->alarm_time, pdata->csr_base + RTC_CMR);
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phytium_rtc_alarm_irq_enable(dev, alrm->enabled);
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return 0;
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}
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static const struct rtc_class_ops phytium_rtc_ops = {
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.read_time = phytium_rtc_read_time,
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.set_mmss = phytium_rtc_set_mmss,
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.read_alarm = phytium_rtc_read_alarm,
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.set_alarm = phytium_rtc_set_alarm,
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.alarm_irq_enable = phytium_rtc_alarm_irq_enable,
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};
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static irqreturn_t phytium_rtc_interrupt(int irq, void *id)
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{
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struct phytium_rtc_dev *pdata = (struct phytium_rtc_dev *) id;
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/* Check if interrupt asserted */
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if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
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return IRQ_NONE;
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/* Clear interrupt */
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readl(pdata->csr_base + RTC_EOI);
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rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
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return IRQ_HANDLED;
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}
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static int phytium_rtc_probe(struct platform_device *pdev)
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{
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struct phytium_rtc_dev *pdata;
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struct resource *res;
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int ret;
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int irq;
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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platform_set_drvdata(pdev, pdata);
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pdata->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pdata->csr_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pdata->csr_base))
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return PTR_ERR(pdata->csr_base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "No IRQ resource\n");
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return irq;
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}
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ret = devm_request_irq(&pdev->dev, irq, phytium_rtc_interrupt, 0,
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dev_name(&pdev->dev), pdata);
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if (ret) {
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dev_err(&pdev->dev, "Could not request IRQ\n");
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return ret;
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}
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#ifndef CONFIG_ACPI
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pdata->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pdata->clk)) {
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dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
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return -ENODEV;
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}
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ret = clk_prepare_enable(pdata->clk);
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if (ret)
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return ret;
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#endif
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spin_lock_init(&spinlock_phytium_rtc);
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/* Turn on the clock and the crystal */
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writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
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ret = device_init_wakeup(&pdev->dev, 1);
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if (ret) {
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clk_disable_unprepare(pdata->clk);
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return ret;
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}
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pdata->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
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&phytium_rtc_ops, THIS_MODULE);
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if (IS_ERR(pdata->rtc)) {
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clk_disable_unprepare(pdata->clk);
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return PTR_ERR(pdata->rtc);
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}
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/* HW does not support update faster than 1 seconds */
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pdata->rtc->uie_unsupported = 1;
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return 0;
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}
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static int phytium_rtc_remove(struct platform_device *pdev)
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{
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struct phytium_rtc_dev *pdata = platform_get_drvdata(pdev);
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phytium_rtc_alarm_irq_enable(&pdev->dev, 0);
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device_init_wakeup(&pdev->dev, 0);
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clk_disable_unprepare(pdata->clk);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int phytium_rtc_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct phytium_rtc_dev *pdata = platform_get_drvdata(pdev);
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int irq;
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/*
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* If this RTC alarm will be used for waking the system up,
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* don't disable it of course. Else we just disable the alarm
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* and await suspension.
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*/
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irq = platform_get_irq(pdev, 0);
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if (device_may_wakeup(&pdev->dev)) {
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if (!enable_irq_wake(irq))
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pdata->irq_wake = 1;
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} else {
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pdata->irq_enabled = phytium_rtc_alarm_irq_enabled(dev);
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phytium_rtc_alarm_irq_enable(dev, 0);
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clk_disable_unprepare(pdata->clk);
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}
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return 0;
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}
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static int phytium_rtc_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct phytium_rtc_dev *pdata = platform_get_drvdata(pdev);
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int irq;
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int rc;
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irq = platform_get_irq(pdev, 0);
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if (device_may_wakeup(&pdev->dev)) {
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if (pdata->irq_wake) {
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disable_irq_wake(irq);
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pdata->irq_wake = 0;
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}
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} else {
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rc = clk_prepare_enable(pdata->clk);
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if (rc) {
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dev_err(dev, "Unable to enable clock error %d\n", rc);
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return rc;
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}
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phytium_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
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}
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(phytium_rtc_pm_ops, phytium_rtc_suspend, phytium_rtc_resume);
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#ifdef CONFIG_OF
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static const struct of_device_id phytium_rtc_of_match[] = {
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{ .compatible = "phytium,rtc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, phytium_rtc_of_match);
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#endif
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#ifdef CONFIG_ACPI
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static const struct acpi_device_id phytium_rtc_acpi_match[] = {
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{ "PHYT0002", 0 },
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{ }
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};
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#endif
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static struct platform_driver phytium_rtc_driver = {
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.probe = phytium_rtc_probe,
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.remove = phytium_rtc_remove,
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.driver = {
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.name = "phytium-rtc",
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.pm = &phytium_rtc_pm_ops,
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.of_match_table = of_match_ptr(phytium_rtc_of_match),
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.acpi_match_table = ACPI_PTR(phytium_rtc_acpi_match),
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},
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};
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module_platform_driver(phytium_rtc_driver);
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MODULE_DESCRIPTION("Phytium RTC driver");
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MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
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MODULE_LICENSE("GPL");
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@ -76,6 +76,7 @@ struct rtc_class_ops {
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int (*ioctl)(struct device *, unsigned int, unsigned long);
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int (*read_time)(struct device *, struct rtc_time *);
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int (*set_time)(struct device *, struct rtc_time *);
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int (*set_mmss)(struct device *, unsigned long secs);
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int (*read_alarm)(struct device *, struct rtc_wkalrm *);
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int (*set_alarm)(struct device *, struct rtc_wkalrm *);
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int (*proc)(struct device *, struct seq_file *);
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