UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/nouveau/volt: convert to new-style nvkm_subdev 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:21 +10:00
parent 31649ecf47
commit 437b2296ce
12 changed files with 164 additions and 256 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
View File

@ -2,20 +2,10 @@
#define __NVKM_VOLT_H__
#include <core/subdev.h>
struct nvkm_voltage {
u32 uv;
u8 id;
};
struct nvkm_volt {
const struct nvkm_volt_func *func;
struct nvkm_subdev subdev;
int (*vid_get)(struct nvkm_volt *);
int (*get)(struct nvkm_volt *);
int (*vid_set)(struct nvkm_volt *, u8 vid);
int (*set)(struct nvkm_volt *, u32 uv);
int (*set_id)(struct nvkm_volt *, u8 id, int condition);
u8 vid_mask;
u8 vid_nr;
struct {
@ -24,35 +14,9 @@ struct nvkm_volt {
} vid[256];
};
static inline struct nvkm_volt *
nvkm_volt(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VOLT);
}
int nvkm_volt_get(struct nvkm_volt *);
int nvkm_volt_set_id(struct nvkm_volt *, u8 id, int condition);
#define nvkm_volt_create(p, e, o, d) \
nvkm_volt_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_volt_destroy(p) ({ \
struct nvkm_volt *v = (p); \
_nvkm_volt_dtor(nv_object(v)); \
})
#define nvkm_volt_init(p) ({ \
struct nvkm_volt *v = (p); \
_nvkm_volt_init(nv_object(v)); \
})
#define nvkm_volt_fini(p,s) \
nvkm_subdev_fini_old((p), (s))
int nvkm_volt_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void _nvkm_volt_dtor(struct nvkm_object *);
int _nvkm_volt_init(struct nvkm_object *);
#define _nvkm_volt_fini _nvkm_subdev_fini
extern struct nvkm_oclass nv40_volt_oclass;
extern struct nvkm_oclass gk20a_volt_oclass;
int nvkm_voltgpio_init(struct nvkm_volt *);
int nvkm_voltgpio_get(struct nvkm_volt *);
int nvkm_voltgpio_set(struct nvkm_volt *, u8);
int nv40_volt_new(struct nvkm_device *, int, struct nvkm_volt **);
int gk20a_volt_new(struct nvkm_device *, int, struct nvkm_volt **);
#endif

92
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -465,7 +465,7 @@ nv40_chipset = {
.mmu = nv04_mmu_new,
.therm = nv40_therm_new,
.timer = nv40_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -490,7 +490,7 @@ nv41_chipset = {
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -515,7 +515,7 @@ nv42_chipset = {
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -540,7 +540,7 @@ nv43_chipset = {
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -565,7 +565,7 @@ nv44_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -590,7 +590,7 @@ nv45_chipset = {
.mmu = nv04_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -615,7 +615,7 @@ nv46_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -640,7 +640,7 @@ nv47_chipset = {
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -665,7 +665,7 @@ nv49_chipset = {
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -690,7 +690,7 @@ nv4a_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -715,7 +715,7 @@ nv4b_chipset = {
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -740,7 +740,7 @@ nv4c_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -765,7 +765,7 @@ nv4e_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -793,7 +793,7 @@ nv50_chipset = {
.mxm = nv50_mxm_new,
.therm = nv50_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv50_disp_new,
// .dma = nv50_dma_new,
// .fifo = nv50_fifo_new,
@ -818,7 +818,7 @@ nv63_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -843,7 +843,7 @@ nv67_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -868,7 +868,7 @@ nv68_chipset = {
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
@ -896,7 +896,7 @@ nv84_chipset = {
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
@ -927,7 +927,7 @@ nv86_chipset = {
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
@ -958,7 +958,7 @@ nv92_chipset = {
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
@ -989,7 +989,7 @@ nv94_chipset = {
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g94_disp_new,
@ -1020,7 +1020,7 @@ nv96_chipset = {
.imem = nv50_instmem_new,
.mmu = nv50_mmu_new,
.bar = g84_bar_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .sw = nv50_sw_new,
@ -1051,7 +1051,7 @@ nv98_chipset = {
.imem = nv50_instmem_new,
.mmu = nv50_mmu_new,
.bar = g84_bar_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .sw = nv50_sw_new,
@ -1082,7 +1082,7 @@ nva0_chipset = {
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = gt200_disp_new,
@ -1114,7 +1114,7 @@ nva3_chipset = {
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
@ -1147,7 +1147,7 @@ nva5_chipset = {
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
@ -1179,7 +1179,7 @@ nva8_chipset = {
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
@ -1210,7 +1210,7 @@ nvaa_chipset = {
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
@ -1241,7 +1241,7 @@ nvac_chipset = {
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
@ -1273,7 +1273,7 @@ nvaf_chipset = {
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
@ -1307,7 +1307,7 @@ nvc0_chipset = {
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
@ -1342,7 +1342,7 @@ nvc1_chipset = {
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
@ -1376,7 +1376,7 @@ nvc3_chipset = {
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
@ -1410,7 +1410,7 @@ nvc4_chipset = {
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
@ -1445,7 +1445,7 @@ nvc8_chipset = {
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
@ -1480,7 +1480,7 @@ nvce_chipset = {
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
@ -1515,7 +1515,7 @@ nvcf_chipset = {
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
@ -1581,7 +1581,7 @@ nvd9_chipset = {
.pmu = gf119_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gf119_disp_new,
// .dma = gf119_dma_new,
@ -1615,7 +1615,7 @@ nve4_chipset = {
.pmu = gk104_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
@ -1651,7 +1651,7 @@ nve6_chipset = {
.pmu = gk104_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
@ -1687,7 +1687,7 @@ nve7_chipset = {
.pmu = gf119_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
@ -1717,7 +1717,7 @@ nvea_chipset = {
.mmu = gf100_mmu_new,
.pmu = gk20a_pmu_new,
.timer = gk20a_timer_new,
// .volt = gk20a_volt_new,
.volt = gk20a_volt_new,
// .ce[2] = gk104_ce2_new,
// .dma = gf119_dma_new,
// .fifo = gk20a_fifo_new,
@ -1747,7 +1747,7 @@ nvf0_chipset = {
.pmu = gk110_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
@ -1783,7 +1783,7 @@ nvf1_chipset = {
.pmu = gk110_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
@ -1819,7 +1819,7 @@ nv106_chipset = {
.pmu = gk208_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
@ -1854,7 +1854,7 @@ nv108_chipset = {
.pmu = gk208_pmu_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
// .volt = nv40_volt_new,
.volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xc0:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -42,7 +41,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -56,7 +54,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -69,7 +66,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -83,7 +79,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -96,7 +91,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -109,7 +103,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -123,7 +116,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xe4:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -43,7 +42,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -58,7 +56,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -79,10 +76,8 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
break;
case 0xf0:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -97,7 +92,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -112,7 +106,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -126,7 +119,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
case 0x108:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;

3
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device)
case 0x117:
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
@ -54,7 +53,6 @@ gm100_identify(struct nvkm_device *device)
/* priv ring says no to 0x10eb14 writes */
#endif
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
@ -76,7 +74,6 @@ gm100_identify(struct nvkm_device *device)
/* priv ring says no to 0x10eb14 writes */
#endif
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x40:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -38,7 +37,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -48,7 +46,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -58,7 +55,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -68,7 +64,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -78,7 +73,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -88,7 +82,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -98,7 +91,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -108,7 +100,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -118,7 +109,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -128,7 +118,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -138,7 +127,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -148,7 +136,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -158,7 +145,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -168,7 +154,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -178,7 +163,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x50:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -38,7 +37,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -51,7 +49,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -64,7 +61,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -77,7 +73,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -90,7 +85,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -103,7 +97,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -116,7 +109,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -129,7 +121,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -142,7 +133,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -155,7 +145,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -169,7 +158,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -182,7 +170,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
@ -195,7 +182,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;

4
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
View File

@ -99,7 +99,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
}
if (volt) {
ret = volt->set_id(volt, cstate->voltage, +1);
ret = nvkm_volt_set_id(volt, cstate->voltage, +1);
if (ret && ret != -ENODEV) {
nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
return ret;
@ -113,7 +113,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
}
if (volt) {
ret = volt->set_id(volt, cstate->voltage, -1);
ret = nvkm_volt_set_id(volt, cstate->voltage, -1);
if (ret && ret != -ENODEV)
nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
}

119
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
View File

@ -21,44 +21,39 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/volt.h>
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bios/vmap.h>
#include <subdev/bios/volt.h>
static int
int
nvkm_volt_get(struct nvkm_volt *volt)
{
if (volt->vid_get) {
int ret = volt->vid_get(volt), i;
if (ret >= 0) {
for (i = 0; i < volt->vid_nr; i++) {
if (volt->vid[i].vid == ret)
return volt->vid[i].uv;
}
ret = -EINVAL;
int ret = volt->func->vid_get(volt), i;
if (ret >= 0) {
for (i = 0; i < volt->vid_nr; i++) {
if (volt->vid[i].vid == ret)
return volt->vid[i].uv;
}
return ret;
ret = -EINVAL;
}
return -ENODEV;
return ret;
}
static int
nvkm_volt_set(struct nvkm_volt *volt, u32 uv)
{
struct nvkm_subdev *subdev = &volt->subdev;
if (volt->vid_set) {
int i, ret = -EINVAL;
for (i = 0; i < volt->vid_nr; i++) {
if (volt->vid[i].uv == uv) {
ret = volt->vid_set(volt, volt->vid[i].vid);
nvkm_debug(subdev, "set %duv: %d\n", uv, ret);
break;
}
int i, ret = -EINVAL;
for (i = 0; i < volt->vid_nr; i++) {
if (volt->vid[i].uv == uv) {
ret = volt->func->vid_set(volt, volt->vid[i].vid);
nvkm_debug(subdev, "set %duv: %d\n", uv, ret);
break;
}
return ret;
}
return -ENODEV;
return ret;
}
static int
@ -83,10 +78,15 @@ nvkm_volt_map(struct nvkm_volt *volt, u8 id)
return id ? id * 10000 : -ENODEV;
}
static int
int
nvkm_volt_set_id(struct nvkm_volt *volt, u8 id, int condition)
{
int ret = nvkm_volt_map(volt, id);
int ret;
if (volt->func->set_id)
return volt->func->set_id(volt, id, condition);
ret = nvkm_volt_map(volt, id);
if (ret >= 0) {
int prev = nvkm_volt_get(volt);
if (!condition || prev < 0 ||
@ -135,53 +135,41 @@ nvkm_volt_parse_bios(struct nvkm_bios *bios, struct nvkm_volt *volt)
}
}
int
_nvkm_volt_init(struct nvkm_object *object)
static int
nvkm_volt_init(struct nvkm_subdev *subdev)
{
struct nvkm_volt *volt = (void *)object;
struct nvkm_subdev *subdev = &volt->subdev;
int ret;
ret = nvkm_subdev_init_old(&volt->subdev);
if (ret)
return ret;
ret = volt->get(volt);
struct nvkm_volt *volt = nvkm_volt(subdev);
int ret = nvkm_volt_get(volt);
if (ret < 0) {
if (ret != -ENODEV)
nvkm_debug(subdev, "current voltage unknown\n");
return 0;
}
nvkm_debug(subdev, "current voltage: %duv\n", ret);
return 0;
}
void
_nvkm_volt_dtor(struct nvkm_object *object)
static void *
nvkm_volt_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_volt *volt = (void *)object;
nvkm_subdev_destroy(&volt->subdev);
return nvkm_volt(subdev);
}
int
nvkm_volt_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, int length, void **pobject)
static const struct nvkm_subdev_func
nvkm_volt = {
.dtor = nvkm_volt_dtor,
.init = nvkm_volt_init,
};
void
nvkm_volt_ctor(const struct nvkm_volt_func *func, struct nvkm_device *device,
int index, struct nvkm_volt *volt)
{
struct nvkm_device *device = (void *)parent;
struct nvkm_bios *bios = device->bios;
struct nvkm_volt *volt;
int ret, i;
int i;
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "VOLT",
"voltage", length, pobject);
volt = *pobject;
if (ret)
return ret;
volt->get = nvkm_volt_get;
volt->set = nvkm_volt_set;
volt->set_id = nvkm_volt_set_id;
nvkm_subdev_ctor(&nvkm_volt, device, index, 0, &volt->subdev);
volt->func = func;
/* Assuming the non-bios device should build the voltage table later */
if (bios)
@ -192,16 +180,15 @@ nvkm_volt_create_(struct nvkm_object *parent, struct nvkm_object *engine,
nvkm_debug(&volt->subdev, "VID %02x: %duv\n",
volt->vid[i].vid, volt->vid[i].uv);
}
/*XXX: this is an assumption.. there probably exists boards
* out there with i2c-connected voltage controllers too..
*/
ret = nvkm_voltgpio_init(volt);
if (ret == 0) {
volt->vid_get = nvkm_voltgpio_get;
volt->vid_set = nvkm_voltgpio_set;
}
}
return ret;
}
int
nvkm_volt_new_(const struct nvkm_volt_func *func, struct nvkm_device *device,
int index, struct nvkm_volt **pvolt)
{
if (!(*pvolt = kzalloc(sizeof(**pvolt), GFP_KERNEL)))
return -ENOMEM;
nvkm_volt_ctor(func, device, index, *pvolt);
return 0;
}

59
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
View File

@ -19,7 +19,9 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <subdev/volt.h>
#define gk20a_volt(p) container_of((p), struct gk20a_volt, base)
#include "priv.h"
#ifdef __KERNEL__
#include <nouveau_platform.h>
#endif
@ -101,9 +103,9 @@ gk20a_volt_calc_voltage(const struct cvb_coef *coef, int speedo)
}
static int
gk20a_volt_vid_get(struct nvkm_volt *obj)
gk20a_volt_vid_get(struct nvkm_volt *base)
{
struct gk20a_volt *volt = container_of(obj, typeof(*volt), base);
struct gk20a_volt *volt = gk20a_volt(base);
int i, uv;
uv = regulator_get_voltage(volt->vdd);
@ -116,9 +118,9 @@ gk20a_volt_vid_get(struct nvkm_volt *obj)
}
static int
gk20a_volt_vid_set(struct nvkm_volt *obj, u8 vid)
gk20a_volt_vid_set(struct nvkm_volt *base, u8 vid)
{
struct gk20a_volt *volt = container_of(obj, typeof(*volt), base);
struct gk20a_volt *volt = gk20a_volt(base);
struct nvkm_subdev *subdev = &volt->base.subdev;
nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv);
@ -126,9 +128,9 @@ gk20a_volt_vid_set(struct nvkm_volt *obj, u8 vid)
}
static int
gk20a_volt_set_id(struct nvkm_volt *obj, u8 id, int condition)
gk20a_volt_set_id(struct nvkm_volt *base, u8 id, int condition)
{
struct gk20a_volt *volt = container_of(obj, typeof(*volt), base);
struct gk20a_volt *volt = gk20a_volt(base);
struct nvkm_subdev *subdev = &volt->base.subdev;
int prev_uv = regulator_get_voltage(volt->vdd);
int target_uv = volt->base.vid[id].uv;
@ -147,27 +149,29 @@ gk20a_volt_set_id(struct nvkm_volt *obj, u8 id, int condition)
return ret;
}
static int
gk20a_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_device *device = (void *)parent;
struct gk20a_volt *volt;
int i, ret, uv;
static const struct nvkm_volt_func
gk20a_volt = {
.vid_get = gk20a_volt_vid_get,
.vid_set = gk20a_volt_vid_set,
.set_id = gk20a_volt_set_id,
};
ret = nvkm_volt_create(parent, engine, oclass, &volt);
*pobject = nv_object(volt);
if (ret)
return ret;
int
gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
{
struct gk20a_volt *volt;
int i, uv;
if (!(volt = kzalloc(sizeof(*volt), GFP_KERNEL)))
return -ENOMEM;
nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base);
*pvolt = &volt->base;
uv = regulator_get_voltage(device->gpu->vdd);
nvkm_info(&volt->base.subdev, "The default voltage is %duV\n", uv);
volt->vdd = device->gpu->vdd;
volt->base.vid_get = gk20a_volt_vid_get;
volt->base.vid_set = gk20a_volt_vid_set;
volt->base.set_id = gk20a_volt_set_id;
volt->base.vid_nr = ARRAY_SIZE(gk20a_cvb_coef);
nvkm_debug(&volt->base.subdev, "%s - vid_nr = %d\n", __func__,
@ -183,14 +187,3 @@ gk20a_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return 0;
}
struct nvkm_oclass
gk20a_volt_oclass = {
.handle = NV_SUBDEV(VOLT, 0xea),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_volt_ctor,
.dtor = _nvkm_volt_dtor,
.init = _nvkm_volt_init,
.fini = _nvkm_volt_fini,
},
};

31
drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
View File

@ -21,31 +21,24 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/volt.h>
#include "priv.h"
static int
nv40_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
static const struct nvkm_volt_func
nv40_volt = {
.vid_get = nvkm_voltgpio_get,
.vid_set = nvkm_voltgpio_set,
};
int
nv40_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
{
struct nvkm_volt *volt;
int ret;
ret = nvkm_volt_create(parent, engine, oclass, &volt);
*pobject = nv_object(volt);
ret = nvkm_volt_new_(&nv40_volt, device, index, &volt);
*pvolt = volt;
if (ret)
return ret;
return 0;
return nvkm_voltgpio_init(volt);
}
struct nvkm_oclass
nv40_volt_oclass = {
.handle = NV_SUBDEV(VOLT, 0x40),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_volt_ctor,
.dtor = _nvkm_volt_dtor,
.init = _nvkm_volt_init,
.fini = _nvkm_volt_fini,
},
};

20
drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h Normal file
View File

@ -0,0 +1,20 @@
#ifndef __NVKM_VOLT_PRIV_H__
#define __NVKM_VOLT_PRIV_H__
#define nvkm_volt(p) container_of((p), struct nvkm_volt, subdev)
#include <subdev/volt.h>
void nvkm_volt_ctor(const struct nvkm_volt_func *, struct nvkm_device *,
int index, struct nvkm_volt *);
int nvkm_volt_new_(const struct nvkm_volt_func *, struct nvkm_device *,
int index, struct nvkm_volt **);
struct nvkm_volt_func {
int (*vid_get)(struct nvkm_volt *);
int (*vid_set)(struct nvkm_volt *, u8 vid);
int (*set_id)(struct nvkm_volt *, u8 id, int condition);
};
int nvkm_voltgpio_init(struct nvkm_volt *);
int nvkm_voltgpio_get(struct nvkm_volt *);
int nvkm_voltgpio_set(struct nvkm_volt *, u8);
#endif