perf/x86/intel/uncore: Expose an Uncore unit to IIO PMON mapping
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Current version supports a server line starting Intel® Xeon® Processor
Scalable Family and introduces mapping for IIO Uncore units only.
Other units can be added on demand.
IIO stack to PMON mapping is exposed through:
/sys/devices/uncore_iio_<pmu_idx>/dieX
where dieX is file which holds "Segment:Root Bus" for PCIe root port,
which can be monitored by that IIO PMON block.
Details are explained in Documentation/ABI/testing/sysfs-devices-mapping
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Alexander Antonov <alexander.antonov@linux.intel.com>
Signed-off-by: Roman Sudarikov <roman.sudarikov@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Link: https://lkml.kernel.org/r/20200601083543.30011-4-alexander.antonov@linux.intel.com
Signed-off-by: Chen Zhuo <sagazchen@tencent.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
This commit is contained in:
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@ -0,0 +1,33 @@
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What: /sys/devices/uncore_iio_x/dieX
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Date: February 2020
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Contact: Roman Sudarikov <roman.sudarikov@linux.intel.com>
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Description:
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Each IIO stack (PCIe root port) has its own IIO PMON block, so
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each dieX file (where X is die number) holds "Segment:Root Bus"
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for PCIe root port, which can be monitored by that IIO PMON
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block.
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For example, on 4-die Xeon platform with up to 6 IIO stacks per
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die and, therefore, 6 IIO PMON blocks per die, the mapping of
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IIO PMON block 0 exposes as the following:
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$ ls /sys/devices/uncore_iio_0/die*
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-r--r--r-- /sys/devices/uncore_iio_0/die0
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-r--r--r-- /sys/devices/uncore_iio_0/die1
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-r--r--r-- /sys/devices/uncore_iio_0/die2
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-r--r--r-- /sys/devices/uncore_iio_0/die3
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$ tail /sys/devices/uncore_iio_0/die*
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==> /sys/devices/uncore_iio_0/die0 <==
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0000:00
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==> /sys/devices/uncore_iio_0/die1 <==
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0000:40
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==> /sys/devices/uncore_iio_0/die2 <==
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0000:80
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==> /sys/devices/uncore_iio_0/die3 <==
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0000:c0
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Which means:
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IIO PMU 0 on die 0 belongs to PCI RP on bus 0x00, domain 0x0000
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IIO PMU 0 on die 1 belongs to PCI RP on bus 0x40, domain 0x0000
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IIO PMU 0 on die 2 belongs to PCI RP on bus 0x80, domain 0x0000
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IIO PMU 0 on die 3 belongs to PCI RP on bus 0xc0, domain 0x0000
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@ -188,6 +188,15 @@ int uncore_pcibus_to_dieid(struct pci_bus *bus);
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ssize_t uncore_event_show(struct device *dev,
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struct device_attribute *attr, char *buf);
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static inline struct intel_uncore_pmu *dev_to_uncore_pmu(struct device *dev)
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{
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return container_of(dev_get_drvdata(dev), struct intel_uncore_pmu, pmu);
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}
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#define to_device_attribute(n) container_of(n, struct device_attribute, attr)
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#define to_dev_ext_attribute(n) container_of(n, struct dev_ext_attribute, attr)
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#define attr_to_ext_attr(n) to_dev_ext_attribute(to_device_attribute(n))
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extern int __uncore_max_dies;
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#define uncore_max_dies() (__uncore_max_dies)
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@ -274,6 +274,30 @@
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#define SKX_CPUNODEID 0xc0
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#define SKX_GIDNIDMAP 0xd4
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/*
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* The CPU_BUS_NUMBER MSR returns the values of the respective CPUBUSNO CSR
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* that BIOS programmed. MSR has package scope.
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* | Bit | Default | Description
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* | [63] | 00h | VALID - When set, indicates the CPU bus
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* numbers have been initialized. (RO)
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* |[62:48]| --- | Reserved
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* |[47:40]| 00h | BUS_NUM_5 — Return the bus number BIOS assigned
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* CPUBUSNO(5). (RO)
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* |[39:32]| 00h | BUS_NUM_4 — Return the bus number BIOS assigned
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* CPUBUSNO(4). (RO)
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* |[31:24]| 00h | BUS_NUM_3 — Return the bus number BIOS assigned
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* CPUBUSNO(3). (RO)
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* |[23:16]| 00h | BUS_NUM_2 — Return the bus number BIOS assigned
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* CPUBUSNO(2). (RO)
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* |[15:8] | 00h | BUS_NUM_1 — Return the bus number BIOS assigned
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* CPUBUSNO(1). (RO)
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* | [7:0] | 00h | BUS_NUM_0 — Return the bus number BIOS assigned
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* CPUBUSNO(0). (RO)
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*/
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#define SKX_MSR_CPU_BUS_NUMBER 0x300
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#define SKX_MSR_CPU_BUS_VALID_BIT (1ULL << 63)
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#define BUS_NUM_STRIDE 8
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/* SKX CHA */
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#define SKX_CHA_MSR_PMON_BOX_FILTER_TID (0x1ffULL << 0)
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#define SKX_CHA_MSR_PMON_BOX_FILTER_LINK (0xfULL << 9)
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@ -3620,6 +3644,170 @@ static struct intel_uncore_ops skx_uncore_iio_ops = {
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.read_counter = uncore_msr_read_counter,
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};
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static inline u8 skx_iio_stack(struct intel_uncore_pmu *pmu, int die)
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{
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return pmu->type->topology[die] >> (pmu->pmu_idx * BUS_NUM_STRIDE);
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}
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static umode_t
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skx_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die)
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{
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struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(kobj_to_dev(kobj));
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/* Root bus 0x00 is valid only for die 0 AND pmu_idx = 0. */
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return (!skx_iio_stack(pmu, die) && pmu->pmu_idx) ? 0 : attr->mode;
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}
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static ssize_t skx_iio_mapping_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_bus *bus = pci_find_next_bus(NULL);
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struct intel_uncore_pmu *uncore_pmu = dev_to_uncore_pmu(dev);
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struct dev_ext_attribute *ea = to_dev_ext_attribute(attr);
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long die = (long)ea->var;
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/*
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* Current implementation is for single segment configuration hence it's
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* safe to take the segment value from the first available root bus.
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*/
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return sprintf(buf, "%04x:%02x\n", pci_domain_nr(bus),
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skx_iio_stack(uncore_pmu, die));
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}
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static int skx_msr_cpu_bus_read(int cpu, u64 *topology)
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{
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u64 msr_value;
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if (rdmsrl_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) ||
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!(msr_value & SKX_MSR_CPU_BUS_VALID_BIT))
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return -ENXIO;
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*topology = msr_value;
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return 0;
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}
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static int die_to_cpu(int die)
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{
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int res = 0, cpu, current_die;
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/*
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* Using cpus_read_lock() to ensure cpu is not going down between
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* looking at cpu_online_mask.
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*/
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cpus_read_lock();
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for_each_online_cpu(cpu) {
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current_die = topology_logical_die_id(cpu);
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if (current_die == die) {
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res = cpu;
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break;
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}
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}
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cpus_read_unlock();
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return res;
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}
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static int skx_iio_get_topology(struct intel_uncore_type *type)
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{
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int i, ret;
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struct pci_bus *bus = NULL;
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/*
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* Verified single-segment environments only; disabled for multiple
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* segment topologies for now except VMD domains.
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* VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
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*/
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while ((bus = pci_find_next_bus(bus))
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&& (!pci_domain_nr(bus) || pci_domain_nr(bus) > 0xffff))
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;
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if (bus)
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return -EPERM;
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type->topology = kcalloc(uncore_max_dies(), sizeof(u64), GFP_KERNEL);
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if (!type->topology)
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return -ENOMEM;
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for (i = 0; i < uncore_max_dies(); i++) {
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ret = skx_msr_cpu_bus_read(die_to_cpu(i), &type->topology[i]);
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if (ret) {
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kfree(type->topology);
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type->topology = NULL;
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return ret;
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}
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}
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return 0;
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}
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static struct attribute_group skx_iio_mapping_group = {
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.is_visible = skx_iio_mapping_visible,
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};
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static const struct attribute_group *skx_iio_attr_update[] = {
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&skx_iio_mapping_group,
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NULL,
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};
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static int skx_iio_set_mapping(struct intel_uncore_type *type)
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{
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char buf[64];
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int ret;
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long die = -1;
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struct attribute **attrs = NULL;
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struct dev_ext_attribute *eas = NULL;
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ret = skx_iio_get_topology(type);
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if (ret)
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return ret;
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/* One more for NULL. */
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attrs = kcalloc((uncore_max_dies() + 1), sizeof(*attrs), GFP_KERNEL);
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if (!attrs)
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goto err;
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eas = kcalloc(uncore_max_dies(), sizeof(*eas), GFP_KERNEL);
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if (!eas)
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goto err;
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for (die = 0; die < uncore_max_dies(); die++) {
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sprintf(buf, "die%ld", die);
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sysfs_attr_init(&eas[die].attr.attr);
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eas[die].attr.attr.name = kstrdup(buf, GFP_KERNEL);
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if (!eas[die].attr.attr.name)
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goto err;
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eas[die].attr.attr.mode = 0444;
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eas[die].attr.show = skx_iio_mapping_show;
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eas[die].attr.store = NULL;
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eas[die].var = (void *)die;
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attrs[die] = &eas[die].attr.attr;
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}
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skx_iio_mapping_group.attrs = attrs;
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return 0;
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err:
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for (; die >= 0; die--)
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kfree(eas[die].attr.attr.name);
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kfree(eas);
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kfree(attrs);
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kfree(type->topology);
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type->attr_update = NULL;
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return -ENOMEM;
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}
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static void skx_iio_cleanup_mapping(struct intel_uncore_type *type)
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{
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struct attribute **attr = skx_iio_mapping_group.attrs;
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if (!attr)
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return;
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for (; *attr; attr++)
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kfree((*attr)->name);
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kfree(attr_to_ext_attr(*skx_iio_mapping_group.attrs));
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kfree(skx_iio_mapping_group.attrs);
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skx_iio_mapping_group.attrs = NULL;
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kfree(type->topology);
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}
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static struct intel_uncore_type skx_uncore_iio = {
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.name = "iio",
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.num_counters = 4,
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.constraints = skx_uncore_iio_constraints,
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.ops = &skx_uncore_iio_ops,
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.format_group = &skx_uncore_iio_format_group,
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.attr_update = skx_iio_attr_update,
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.set_mapping = skx_iio_set_mapping,
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.cleanup_mapping = skx_iio_cleanup_mapping,
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};
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enum perf_uncore_iio_freerunning_type_id {
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