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pinctrl: renesas: r8a779g0: Fixup MODSEL8 

MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is
indicating that I2C needs 1.  But we should use 0 for all cases in
reality.  New Datasheet should be updated.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto 2022-07-01 01:36:51 +00:00 committed by Geert Uytterhoeven
parent 050442ae4c
commit 42cbd16e7c
1 changed files with 12 additions and 12 deletions
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24
drivers/pinctrl/renesas/pfc-r8a779g0.c
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@ -1167,29 +1167,29 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV), PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
/* IP0SR8 */ /* IP0SR8 */
PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_1), PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_1), PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_1), PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_1), PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_1), PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_1), PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_1), PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_1), PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
/* IP1SR8 */ /* IP1SR8 */
PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_1), PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0), PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0), PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_1), PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),
PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0), PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0), PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_1), PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),
PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0), PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0), PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_1), PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),
PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0), PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N), PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),