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msm:disp:dpu1: add mixer selection for display topology 

mixer selection in the display topology is based on multiple
factors
1) mixers available in the hw
2) interfaces to be enabled
3) merge capability

change will pickup mixer as per the topology need.

Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Kalyan Thota 2019-11-25 17:29:29 +05:30 committed by Rob Clark
parent 73bfb790ac
commit 42a558b71c
3 changed files with 21 additions and 3 deletions
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21
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
View File

@ -58,7 +58,7 @@
#define IDLE_SHORT_TIMEOUT 1
#define MAX_VDISPLAY_SPLIT 1080
#define MAX_HDISPLAY_SPLIT 1080
/* timeout in frames waiting for frame done */
#define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
@ -534,8 +534,23 @@ static struct msm_display_topology dpu_encoder_get_topology(
if (dpu_enc->phys_encs[i])
intf_count++;
/* User split topology for width > 1080 */
topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
/* Datapath topology selection
*
* Dual display
* 2 LM, 2 INTF ( Split display using 2 interfaces)
*
* Single display
* 1 LM, 1 INTF
* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
*
*/
if (intf_count == 2)
topology.num_lm = 2;
else if (!dpu_kms->catalog->caps->has_3d_merge)
topology.num_lm = 1;
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
topology.num_enc = 0;
topology.num_intf = intf_count;

1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View File

@ -67,6 +67,7 @@ static const struct dpu_caps sdm845_dpu_caps = {
.has_src_split = true,
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
};
static const struct dpu_caps sc7180_dpu_caps = {

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@ -287,6 +287,7 @@ struct dpu_qos_lut_tbl {
* @has_src_split source split feature status
* @has_dim_layer dim layer feature status
* @has_idle_pc indicate if idle power collapse feature is supported
* @has_3d_merge indicate if 3D merge is supported
*/
struct dpu_caps {
u32 max_mixer_width;
@ -297,6 +298,7 @@ struct dpu_caps {
bool has_src_split;
bool has_dim_layer;
bool has_idle_pc;
bool has_3d_merge;
};
/**