drm/amdgpu: add powerplay sclk OD support through sysfs (v2)
Add a new sysfs entry pp_sclk_od to support sclk overdrive(OD) overclocking, the entry is read/write, the value of input/output is an integer which is the over percentage of the highest sclk. v2: drop extra semicolon Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b2ea0dcd27
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428bafa86c
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@ -2342,6 +2342,12 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_dpm_force_clock_level(adev, type, level) \
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(adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
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#define amdgpu_dpm_get_sclk_od(adev) \
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(adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
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#define amdgpu_dpm_set_sclk_od(adev, value) \
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(adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
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#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
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(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
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@ -469,6 +469,46 @@ fail:
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return count;
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}
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static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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uint32_t value = 0;
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if (adev->pp_enabled)
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value = amdgpu_dpm_get_sclk_od(adev);
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return snprintf(buf, PAGE_SIZE, "%d\n", value);
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}
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static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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int ret;
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long int value;
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ret = kstrtol(buf, 0, &value);
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if (ret) {
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count = -EINVAL;
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goto fail;
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}
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if (adev->pp_enabled)
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amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
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amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
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fail:
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return count;
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}
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static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
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static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
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amdgpu_get_dpm_forced_performance_level,
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@ -490,6 +530,9 @@ static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
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static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
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amdgpu_get_pp_dpm_pcie,
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amdgpu_set_pp_dpm_pcie);
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static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
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amdgpu_get_pp_sclk_od,
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amdgpu_set_pp_sclk_od);
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static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
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struct device_attribute *attr,
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@ -1123,6 +1166,11 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
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DRM_ERROR("failed to create device file pp_dpm_pcie\n");
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return ret;
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}
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ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
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if (ret) {
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DRM_ERROR("failed to create device file pp_sclk_od\n");
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return ret;
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}
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}
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ret = amdgpu_debugfs_pm_init(adev);
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if (ret) {
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@ -1149,6 +1197,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
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device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
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device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
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device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
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device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
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}
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}
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@ -536,6 +536,10 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
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case AMD_PP_EVENT_COMPLETE_INIT:
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ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
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break;
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case AMD_PP_EVENT_READJUST_POWER_STATE:
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pp_handle->hwmgr->current_ps = pp_handle->hwmgr->boot_ps;
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ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
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break;
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default:
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break;
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}
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@ -806,6 +810,44 @@ static int pp_dpm_print_clock_levels(void *handle,
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return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
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}
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static int pp_dpm_get_sclk_od(void *handle)
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{
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struct pp_hwmgr *hwmgr;
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if (!handle)
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return -EINVAL;
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hwmgr = ((struct pp_instance *)handle)->hwmgr;
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PP_CHECK_HW(hwmgr);
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if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
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printk(KERN_INFO "%s was not implemented.\n", __func__);
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return 0;
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}
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return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
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}
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static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
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{
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struct pp_hwmgr *hwmgr;
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if (!handle)
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return -EINVAL;
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hwmgr = ((struct pp_instance *)handle)->hwmgr;
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PP_CHECK_HW(hwmgr);
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if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
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printk(KERN_INFO "%s was not implemented.\n", __func__);
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return 0;
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}
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return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
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}
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const struct amd_powerplay_funcs pp_dpm_funcs = {
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.get_temperature = pp_dpm_get_temperature,
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.load_firmware = pp_dpm_load_fw,
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@ -828,6 +870,8 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
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.set_pp_table = pp_dpm_set_pp_table,
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.force_clock_level = pp_dpm_force_clock_level,
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.print_clock_levels = pp_dpm_print_clock_levels,
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.get_sclk_od = pp_dpm_get_sclk_od,
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.set_sclk_od = pp_dpm_set_sclk_od,
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};
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static int amd_pp_instance_init(struct amd_pp_init *pp_init,
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@ -342,6 +342,8 @@ struct amd_powerplay_funcs {
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int (*set_pp_table)(void *handle, const char *buf, size_t size);
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int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
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int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
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int (*get_sclk_od)(void *handle);
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int (*set_sclk_od)(void *handle, uint32_t value);
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};
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struct amd_powerplay {
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@ -338,6 +338,8 @@ struct pp_hwmgr_func {
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int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
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int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
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int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
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int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
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int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
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};
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struct pp_table_func {
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