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Introduce MediaTek regulator coupler driver to ensure that the SRAM 

voltage in par with the GPU voltage. This allows for a stable use of the
 GPU.
 
 mtk-mutex:
 - add support for MT8188 vdosys0 path
 - allow it to be build as module
 - add support for MT8195 vdosys1 path
 
 mmsys:
 - add MT8188 vdosys0 path
 - allow to be build as a module
 - add MT8195 vdosys1 path
 - add support for CMDQ
 - allow for up to 64 reset bits
 - add supprot for the MT8195 vppsys[0,1] pathes
 
 pm-domains:
 - keep power for the MT8186 ADSP on by default
 - add support for MT8188
 - add support for buck isolation needed in specific pm-domains for
   MT8188 and MT8192
 
 mtk-svs:
 - enable IRQ later to allow using kexec
 - several improvments on the code base
 - fix modalias
 
 pmic wrapper:
 - convert binding to yaml. As this is thightly coupled to the MT6357
   PMIC, I took patches regarding it as well.
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmPaoLsXHG1hdHRoaWFz
 LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH44bw//Wpo6qdxzTOOEGkzdD7JairN5
 ozPZyIiSTcg+zVWNJ5sbMMe3xtjIXJVpzI3yfJtx4BTtjns1FNsLeLpVKrS1RVd+
 fiSAmhrioYUHk7H599tArs4H+5h1lJkcpf1X+7fX5mc9yCQSsAmAcVeFA5TMbKpS
 wdr460r7sUZtSLSVLHza1R7k4V3OLHzMzSztBTtgryE/rV9y/1rQ3hb8aiEgu4h1
 5igUDXJfzsmGc45UxCaWZnrziREhSMWe0kc4eGDQSGL6Nc/mjZ9wjhDDnzfcwDTE
 mkvTEAgiS6Jh/hoqHmwyzTO3lZRTIxOc/d5eKTzwk3z7fglGt35wN6jJRHC7Utwx
 aSt4x8R+3CrlUaAY2FC/1oxt3ONbcLqxPGVUTbvQYxCeXSTagEok1PxyKZZl1bKe
 XYbJfm0q9tujxItgbF79j6UD0eWVZ9/UM68gkiaUfZ3AYQdLh9J7nqPScu6UqRR5
 5gCeLm41/BOrnObmpv0g6VcGfpIjej8gfJinDLgcjUMW8nv38UpglUojeFJutT7b
 BGMmSC/GR57d2NmhGkWSgdYsjrU6iADf936WdKSSfYswkxrOWLgYSd41bym1fluK
 JxUYJga4S6Xu3Pjj9vbX60Vi7d9LitEuyAQbi540TP148NjBs0d29puhOGK8USPh
 z+Jaoaj+j6XSSg0fotQ=
 =8+S0
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmPdCowACgkQmmx57+YA
 GNknYQ//X3Eg6K4AM3EJ2eKuVyVbqChPwTo1SGgyKb2GpTCvkHlb9yNfKe+LluA8
 /KLm7bmvpyTA0yegXmjMNo0HmHw5Qu5wsWTdb74JifAWaH9kh+8AGRptFZO+4bzx
 /Twj3ZkqqTqzI+NETRcL13sVIEE8y+iGRBVUi8kIxQVS7BYbuBUc0gkgEfbYEfIB
 sLa+swF9NT/h8cd0jg4TJqTL3F6pUr28JzGcg5fs5JH0WqSkbxELJcW65x73OCdW
 RjU9ioLVKDjFq6m/6KEq7QzWb35ebItG4yLSH6nwT9l7B/KV9pC0TIapiKLlne0N
 HlerHU512ynbvtSo+8zyL+gKGiPvQqxyLb/Sd669edSqeCASi8dlKcwxT/boldzu
 JZLf7qBJR5X8BLrFp8RhWs2D3Mockq8aXc4WGNPnzuvOvRQrl5sfkH8spl2pjkT+
 rd6i77IWd+munKldZzFwwDlAhvmpPFWA1F3ogViFiLsy17UwId2AO37FGPbtZ7BL
 xqJIkLAqfXqUri6KM/MFC5njbWimIfDKmsmQ+FA8DMO7+OFnnNEVKewp63XcOv+m
 mXkUzoMHnG6GB7tQie5AbwD4RKE14Rr1uiYZRRfdht+zreYYEvqfbowU2dL3OTnr
 EVnXNSUChOKfW4OBUrX6nKbvni0ffzRaC+aLyBdE8yqMCr7v1RA=
 =fPm5
 -----END PGP SIGNATURE-----

Merge tag 'v6.2-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/drivers

Introduce MediaTek regulator coupler driver to ensure that the SRAM
voltage in par with the GPU voltage. This allows for a stable use of the
GPU.

mtk-mutex:
- add support for MT8188 vdosys0 path
- allow it to be build as module
- add support for MT8195 vdosys1 path

mmsys:
- add MT8188 vdosys0 path
- allow to be build as a module
- add MT8195 vdosys1 path
- add support for CMDQ
- allow for up to 64 reset bits
- add supprot for the MT8195 vppsys[0,1] pathes

pm-domains:
- keep power for the MT8186 ADSP on by default
- add support for MT8188
- add support for buck isolation needed in specific pm-domains for
  MT8188 and MT8192

mtk-svs:
- enable IRQ later to allow using kexec
- several improvments on the code base
- fix modalias

pmic wrapper:
- convert binding to yaml. As this is thightly coupled to the MT6357
  PMIC, I took patches regarding it as well.

* tag 'v6.2-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (41 commits)
  soc: mediatek: mtk-svs: add missing MODULE_DEVICE_TABLE
  soc: mediatek: mtk-devapc: Switch to devm_clk_get_enabled()
  soc: mtk-svs: mt8183: refactor o_slope calculation
  soc: mediatek: mtk-svs: delete superfluous platform data entries
  soc: mediatek: mtk-svs: move svs_platform_probe into probe
  soc: mediatek: mtk-svs: improve readability of platform_probe
  soc: mediatek: mtk-svs: clean up platform probing
  soc: mediatek: mtk-svs: keep svs alive if CONFIG_DEBUG_FS not supported
  soc: mediatek: mtk-svs: Use pm_runtime_resume_and_get() in svs_init01()
  soc: mediatek: mtk-svs: reset svs when svs_resume() fail
  soc: mediatek: mtk-svs: restore default voltages when svs_init02() fail
  soc: mediatek: mmsys: add support for MT8195 VPPSYS
  dt-bindings: arm: mediatek: mmsys: Add support for MT8195 VPPSYS
  soc: mediatek: Introduce mediatek-regulator-coupler driver
  soc: mediatek: mtk-svs: Enable the IRQ later
  soc: mediatek: add mtk-mutex support for mt8195 vdosys1
  soc: mediatek: add mtk-mutex component - dp_intf1
  soc: mediatek: mmsys: add reset control for MT8195 vdosys1
  soc: mediatek: mmsys: add mmsys for support 64 reset bits
  soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
  ...

Link: https://lore.kernel.org/r/396d51fc-81f3-4a2b-d7a7-b966bfe3002a@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-02-03 14:22:02 +01:00
parent a64c36b8b7 6f42f5e73b
commit 426082a214
28 changed files with 1987 additions and 222 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View File

@ -31,7 +31,11 @@ properties:
- mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0
- mediatek,mt8195-vppsys1
- mediatek,mt8365-mmsys
- const: syscon

1
Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml
View File

@ -26,6 +26,7 @@ properties:
enum:
- mediatek,mt6323-keys
- mediatek,mt6331-keys
- mediatek,mt6357-keys
- mediatek,mt6358-keys
- mediatek,mt6397-keys

2
Documentation/devicetree/bindings/leds/leds-mt6323.txt
View File

@ -9,7 +9,7 @@ MT6323 PMIC hardware.
For MT6323 MFD bindings see:
Documentation/devicetree/bindings/mfd/mt6397.txt
For MediaTek PMIC wrapper bindings see:
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
Required properties:
- compatible : Must be "mediatek,mt6323-led"

111
Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml Normal file
View File

@ -0,0 +1,111 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT6357 PMIC
maintainers:
- Flora Fu <flora.fu@mediatek.com>
- Alexandre Mergnat <amergnat@baylibre.com>
description: |
MT6357 is a power management system chip containing 5 buck
converters and 29 LDOs. Supported features are audio codec,
USB battery charging, fuel gauge, RTC
This is a multifunction device with the following sub modules:
- Regulator
- RTC
- Keys
It is interfaced to host controller using SPI interface by a proprietary hardware
called PMIC wrapper or pwrap. This MFD is a child device of pwrap.
See the following for pwrap node definitions:
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
properties:
compatible:
const: mediatek,mt6357
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
regulators:
type: object
$ref: /schemas/regulator/mediatek,mt6357-regulator.yaml
description:
List of MT6357 BUCKs and LDOs regulators.
rtc:
type: object
$ref: /schemas/rtc/rtc.yaml#
description:
MT6357 Real Time Clock.
properties:
compatible:
const: mediatek,mt6357-rtc
start-year: true
required:
- compatible
keys:
type: object
$ref: /schemas/input/mediatek,pmic-keys.yaml
description:
MT6357 power and home keys.
required:
- compatible
- regulators
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pwrap {
pmic {
compatible = "mediatek,mt6357";
interrupt-parent = <&pio>;
interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
regulators {
mt6357_vproc_reg: buck-vproc {
regulator-name = "vproc";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <220>;
regulator-always-on;
};
// ...
mt6357_vusb33_reg: ldo-vusb33 {
regulator-name = "vusb33";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <264>;
};
};
rtc {
compatible = "mediatek,mt6357-rtc";
};
keys {
compatible = "mediatek,mt6357-keys";
};
};
};

2
Documentation/devicetree/bindings/mfd/mt6397.txt
View File

@ -13,7 +13,7 @@ MT6397/MT6323 is a multifunction device with the following sub modules:
It is interfaced to host controller using SPI interface by a proprietary hardware
called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
See the following for pwarp node definitions:
../soc/mediatek/pwrap.txt
../soc/mediatek/mediatek,pwrap.yaml
This document describes the binding for MFD device and its sub module.

2
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
View File

@ -28,6 +28,7 @@ properties:
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
- mediatek,mt8186-power-controller
- mediatek,mt8188-power-controller
- mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
@ -84,6 +85,7 @@ $defs:
"include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
"include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
maxItems: 1

1
Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
View File

@ -32,6 +32,7 @@ properties:
- mediatek,mt8183-disp-mutex
- mediatek,mt8186-disp-mutex
- mediatek,mt8186-mdp3-mutex
- mediatek,mt8188-disp-mutex
- mediatek,mt8192-disp-mutex
- mediatek,mt8195-disp-mutex

147
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml Normal file
View File

@ -0,0 +1,147 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek PMIC Wrapper
maintainers:
- Flora Fu <flora.fu@mediatek.com>
- Alexandre Mergnat <amergnat@baylibre.com>
description:
On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
is not directly visible to the CPU, but only through the PMIC wrapper
inside the SoC. The communication between the SoC and the PMIC can
optionally be encrypted. Also a non standard Dual IO SPI mode can be
used to increase speed.
IP Pairing
On MT8135 the pins of some SoC internal peripherals can be on the PMIC.
The signals of these pins are routed over the SPI bus using the pwrap
bridge. In the binding description below the properties needed for bridging
are marked with "IP Pairing". These are optional on SoCs which do not support
IP Pairing
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-pwrap
- mediatek,mt6765-pwrap
- mediatek,mt6779-pwrap
- mediatek,mt6797-pwrap
- mediatek,mt6873-pwrap
- mediatek,mt7622-pwrap
- mediatek,mt8135-pwrap
- mediatek,mt8173-pwrap
- mediatek,mt8183-pwrap
- mediatek,mt8186-pwrap
- mediatek,mt8188-pwrap
- mediatek,mt8195-pwrap
- mediatek,mt8365-pwrap
- mediatek,mt8516-pwrap
- items:
- enum:
- mediatek,mt8186-pwrap
- mediatek,mt8195-pwrap
- const: syscon
reg:
minItems: 1
items:
- description: PMIC wrapper registers
- description: IP pairing registers
reg-names:
minItems: 1
items:
- const: pwrap
- const: pwrap-bridge
interrupts:
maxItems: 1
clocks:
minItems: 2
items:
- description: SPI bus clock
- description: Main module clock
- description: System module clock
- description: Timer module clock
clock-names:
minItems: 2
items:
- const: spi
- const: wrap
- const: sys
- const: tmr
resets:
minItems: 1
items:
- description: PMIC wrapper reset
- description: IP pairing reset
reset-names:
minItems: 1
items:
- const: pwrap
- const: pwrap-bridge
pmic:
type: object
required:
- compatible
- reg
- reg-names
- interrupts
- clocks
- clock-names
dependentRequired:
resets: [reset-names]
allOf:
- if:
properties:
compatible:
contains:
const: mediatek,mt8365-pwrap
then:
properties:
clocks:
minItems: 4
clock-names:
minItems: 4
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt8135-resets.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pwrap@1000f000 {
compatible = "mediatek,mt8135-pwrap";
reg = <0 0x1000f000 0 0x1000>,
<0 0x11017000 0 0x1000>;
reg-names = "pwrap", "pwrap-bridge";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "spi", "wrap";
resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
reset-names = "pwrap", "pwrap-bridge";
};
};

75
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
View File

@ -1,75 +0,0 @@
MediaTek PMIC Wrapper Driver
This document describes the binding for the MediaTek PMIC wrapper.
On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
is not directly visible to the CPU, but only through the PMIC wrapper
inside the SoC. The communication between the SoC and the PMIC can
optionally be encrypted. Also a non standard Dual IO SPI mode can be
used to increase speed.
IP Pairing
on MT8135 the pins of some SoC internal peripherals can be on the PMIC.
The signals of these pins are routed over the SPI bus using the pwrap
bridge. In the binding description below the properties needed for bridging
are marked with "IP Pairing". These are optional on SoCs which do not support
IP Pairing
Required properties in pwrap device node.
- compatible:
"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
"mediatek,mt6765-pwrap" for MT6765 SoCs
"mediatek,mt6779-pwrap" for MT6779 SoCs
"mediatek,mt6797-pwrap" for MT6797 SoCs
"mediatek,mt6873-pwrap" for MT6873/8192 SoCs
"mediatek,mt7622-pwrap" for MT7622 SoCs
"mediatek,mt8135-pwrap" for MT8135 SoCs
"mediatek,mt8173-pwrap" for MT8173 SoCs
"mediatek,mt8183-pwrap" for MT8183 SoCs
"mediatek,mt8186-pwrap" for MT8186 SoCs
"mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs
"mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8365-pwrap" for MT8365 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: "pwrap" is required; "pwrap-bridge" is optional.
"pwrap": Main registers base
"pwrap-bridge": bridge base (IP Pairing)
- reg: Must contain an entry for each entry in reg-names.
- clock-names: Must include the following entries:
"spi": SPI bus clock
"wrap": Main module clock
"sys": Optional system module clock
"tmr": Optional timer module clock
- clocks: Must contain an entry for each entry in clock-names.
Optional properities:
- reset-names: Some SoCs include the following entries:
"pwrap"
"pwrap-bridge" (IP Pairing)
- resets: Must contain an entry for each entry in reset-names.
- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
See the following for child node definitions:
Documentation/devicetree/bindings/mfd/mt6397.txt
or the regulator-only device as the child device of pwrap, such as MT6380.
See the following definitions for such kinds of devices.
Documentation/devicetree/bindings/regulator/mt6380-regulator.txt
Example:
pwrap: pwrap@1000f000 {
compatible = "mediatek,mt8135-pwrap";
reg = <0 0x1000f000 0 0x1000>,
<0 0x11017000 0 0x1000>;
reg-names = "pwrap", "pwrap-bridge";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
reset-names = "pwrap", "pwrap-bridge";
clocks = <&clk26m>, <&clk26m>;
clock-names = "spi", "wrap";
pmic {
compatible = "mediatek,mt6397";
};
};

17
drivers/input/keyboard/mtk-pmic-keys.c
View File

@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6357/registers.h>
#include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6397/registers.h>
@ -90,6 +91,19 @@ static const struct mtk_pmic_regs mt6331_regs = {
.rst_lprst_mask = MTK_PMIC_MT6331_RST_DU_MASK,
};
static const struct mtk_pmic_regs mt6357_regs = {
.keys_regs[MTK_PMIC_PWRKEY_INDEX] =
MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS,
0x2, MT6357_PSC_TOP_INT_CON0, 0x5,
MTK_PMIC_PWRKEY_RST),
.keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS,
0x8, MT6357_PSC_TOP_INT_CON0, 0xa,
MTK_PMIC_HOMEKEY_INDEX),
.pmic_rst_reg = MT6357_TOP_RST_MISC,
.rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
};
static const struct mtk_pmic_regs mt6358_regs = {
.keys_regs[MTK_PMIC_PWRKEY_INDEX] =
MTK_PMIC_KEYS_REGS(MT6358_TOPSTATUS,
@ -276,6 +290,9 @@ static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = {
}, {
.compatible = "mediatek,mt6331-keys",
.data = &mt6331_regs,
}, {
.compatible = "mediatek,mt6357-keys",
.data = &mt6357_regs,
}, {
.compatible = "mediatek,mt6358-keys",
.data = &mt6358_regs,

7
drivers/soc/mediatek/Kconfig
View File

@ -44,6 +44,11 @@ config MTK_PMIC_WRAP
on different MediaTek SoCs. The PMIC wrapper is a proprietary
hardware to connect the PMIC.
config MTK_REGULATOR_COUPLER
bool "MediaTek SoC Regulator Coupler" if COMPILE_TEST
default ARCH_MEDIATEK
depends on REGULATOR
config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
default ARCH_MEDIATEK
@ -68,7 +73,7 @@ config MTK_SCPSYS_PM_DOMAINS
tasks in the system.
config MTK_MMSYS
bool "MediaTek MMSYS Support"
tristate "MediaTek MMSYS Support"
default ARCH_MEDIATEK
depends on HAS_IOMEM
help

1
drivers/soc/mediatek/Makefile
View File

@ -3,6 +3,7 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_REGULATOR_COUPLER) += mtk-regulator-coupler.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o

4
drivers/soc/mediatek/mt8186-pm-domains.h
View File

@ -304,7 +304,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.ctl_offs = 0x9FC,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_ADSP_INFRA] = {
.name = "adsp_infra",
@ -312,7 +311,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
.ctl_offs = 0x9F8,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_ADSP_TOP] = {
.name = "adsp_top",
@ -332,7 +330,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
MT8186_TOP_AXI_PROT_EN_3_CLR,
MT8186_TOP_AXI_PROT_EN_3_STA),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
};

149
drivers/soc/mediatek/mt8188-mmsys.h Normal file
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@ -0,0 +1,149 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
#define __SOC_MEDIATEK_MT8188_MMSYS_H
#define MT8188_VDO0_OVL_MOUT_EN 0xf14
#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
#define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
#define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
#define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
#define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
#define MT8188_VDO0_SEL_IN 0xf34
#define MT8188_VDO0_SEL_OUT 0xf38
#define MT8188_VDO0_DISP_RDMA_SEL 0xf40
#define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0)
#define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0)
#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0)
#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0)
#define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK GENMASK(8, 8)
#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 (0 << 8)
#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0 (1 << 8)
#define MT8188_VDO0_DSI0_SEL_IN 0xf44
#define MT8188_SEL_IN_DSI0_FROM_MASK BIT(0)
#define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 0)
#define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 0)
#define MT8188_VDO0_DP_INTF0_SEL_IN 0xf4C
#define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0)
#define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT (0 << 0)
#define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 0)
#define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 (3 << 0)
#define MT8188_VDO0_DISP_DITHER0_SEL_OUT 0xf58
#define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0)
#define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
#define MT8188_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
#define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 (6 << 0)
#define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 (7 << 0)
#define MT8188_VDO0_VPP_MERGE_SEL 0xf60
#define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
#define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
#define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT (3 << 0)
#define MT8188_SOUT_VPP_MERGE_TO_MASK GENMASK(6, 4)
#define MT8188_SOUT_VPP_MERGE_TO_DSI1 (0 << 4)
#define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 4)
#define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 4)
#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 4)
#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 4)
#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 (5 << 4)
#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
#define MT8188_VDO0_DSC_WARP_SEL 0xf64
#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0)
#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 (0 << 0)
#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE (1 << 0)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(19, 16)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 BIT(16)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(17)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19)
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8188_VDO0_DSC_WARP_SEL,
MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK,
MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT,
MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DSI0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT,
MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DP_INTF0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
},
};
#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */

623
drivers/soc/mediatek/mt8188-pm-domains.h Normal file
View File

@ -0,0 +1,623 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <garmin.chang@mediatek.com>
*/
#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
#include "mtk-pm-domains.h"
#include <dt-bindings/power/mediatek,mt8188-power.h>
/*
* MT8188 power domain support
*/
static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
[MT8188_POWER_DOMAIN_MFG0] = {
.name = "mfg0",
.sta_mask = BIT(1),
.ctl_offs = 0x300,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8188_POWER_DOMAIN_MFG1] = {
.name = "mfg1",
.sta_mask = BIT(2),
.ctl_offs = 0x304,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
MT8188_TOP_AXI_PROT_EN_SET,
MT8188_TOP_AXI_PROT_EN_CLR,
MT8188_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
MT8188_TOP_AXI_PROT_EN_1_SET,
MT8188_TOP_AXI_PROT_EN_1_CLR,
MT8188_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
MT8188_TOP_AXI_PROT_EN_SET,
MT8188_TOP_AXI_PROT_EN_CLR,
MT8188_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8188_POWER_DOMAIN_MFG2] = {
.name = "mfg2",
.sta_mask = BIT(3),
.ctl_offs = 0x308,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_MFG3] = {
.name = "mfg3",
.sta_mask = BIT(4),
.ctl_offs = 0x30C,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_MFG4] = {
.name = "mfg4",
.sta_mask = BIT(5),
.ctl_offs = 0x310,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = {
.name = "pextp_mac_p0",
.sta_mask = BIT(10),
.ctl_offs = 0x324,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
MT8188_TOP_AXI_PROT_EN_SET,
MT8188_TOP_AXI_PROT_EN_CLR,
MT8188_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = {
.name = "pextp_phy_top",
.sta_mask = BIT(12),
.ctl_offs = 0x328,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_CSIRX_TOP] = {
.name = "pextp_csirx_top",
.sta_mask = BIT(17),
.ctl_offs = 0x3C4,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_ETHER] = {
.name = "ether",
.sta_mask = BIT(1),
.ctl_offs = 0x338,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8188_POWER_DOMAIN_HDMI_TX] = {
.name = "hdmi_tx",
.sta_mask = BIT(18),
.ctl_offs = 0x37C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8188_POWER_DOMAIN_ADSP_AO] = {
.name = "adsp_ao",
.sta_mask = BIT(10),
.ctl_offs = 0x35C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_ALWAYS_ON,
},
[MT8188_POWER_DOMAIN_ADSP_INFRA] = {
.name = "adsp_infra",
.sta_mask = BIT(9),
.ctl_offs = 0x358,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON,
},
[MT8188_POWER_DOMAIN_ADSP] = {
.name = "adsp",
.sta_mask = BIT(8),
.ctl_offs = 0x354,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8188_POWER_DOMAIN_AUDIO] = {
.name = "audio",
.sta_mask = BIT(6),
.ctl_offs = 0x34C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8188_POWER_DOMAIN_AUDIO_ASRC] = {
.name = "audio_asrc",
.sta_mask = BIT(7),
.ctl_offs = 0x350,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_VPPSYS0] = {
.name = "vppsys0",
.sta_mask = BIT(11),
.ctl_offs = 0x360,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
MT8188_TOP_AXI_PROT_EN_SET,
MT8188_TOP_AXI_PROT_EN_CLR,
MT8188_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
MT8188_TOP_AXI_PROT_EN_SET,
MT8188_TOP_AXI_PROT_EN_CLR,
MT8188_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
},
[MT8188_POWER_DOMAIN_VDOSYS0] = {
.name = "vdosys0",
.sta_mask = BIT(13),
.ctl_offs = 0x368,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
MT8188_TOP_AXI_PROT_EN_SET,
MT8188_TOP_AXI_PROT_EN_CLR,
MT8188_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
},
},
[MT8188_POWER_DOMAIN_VDOSYS1] = {
.name = "vdosys1",
.sta_mask = BIT(14),
.ctl_offs = 0x36C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
},
[MT8188_POWER_DOMAIN_DP_TX] = {
.name = "dp_tx",
.sta_mask = BIT(16),
.ctl_offs = 0x374,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_EDP_TX] = {
.name = "edp_tx",
.sta_mask = BIT(17),
.ctl_offs = 0x378,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_VPPSYS1] = {
.name = "vppsys1",
.sta_mask = BIT(12),
.ctl_offs = 0x364,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
},
[MT8188_POWER_DOMAIN_WPE] = {
.name = "wpe",
.sta_mask = BIT(15),
.ctl_offs = 0x370,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_VDEC0] = {
.name = "vdec0",
.sta_mask = BIT(19),
.ctl_offs = 0x380,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_VDEC1] = {
.name = "vdec1",
.sta_mask = BIT(20),
.ctl_offs = 0x384,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_VENC] = {
.name = "venc",
.sta_mask = BIT(22),
.ctl_offs = 0x38C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_IMG_VCORE] = {
.name = "vcore",
.sta_mask = BIT(28),
.ctl_offs = 0x3A4,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8188_POWER_DOMAIN_IMG_MAIN] = {
.name = "img_main",
.sta_mask = BIT(29),
.ctl_offs = 0x3A8,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_DIP] = {
.name = "dip",
.sta_mask = BIT(30),
.ctl_offs = 0x3AC,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_IPE] = {
.name = "ipe",
.sta_mask = BIT(31),
.ctl_offs = 0x3B0,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_CAM_VCORE] = {
.name = "cam_vcore",
.sta_mask = BIT(27),
.ctl_offs = 0x3A0,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
MT8188_TOP_AXI_PROT_EN_1_SET,
MT8188_TOP_AXI_PROT_EN_1_CLR,
MT8188_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
MT8188_TOP_AXI_PROT_EN_MM_SET,
MT8188_TOP_AXI_PROT_EN_MM_CLR,
MT8188_TOP_AXI_PROT_EN_MM_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8188_POWER_DOMAIN_CAM_MAIN] = {
.name = "cam_main",
.sta_mask = BIT(24),
.ctl_offs = 0x394,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
MT8188_TOP_AXI_PROT_EN_2_SET,
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_CAM_SUBA] = {
.name = "cam_suba",
.sta_mask = BIT(25),
.ctl_offs = 0x398,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_CAM_SUBB] = {
.name = "cam_subb",
.sta_mask = BIT(26),
.ctl_offs = 0x39C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
};
static const struct scpsys_soc_data mt8188_scpsys_data = {
.domains_data = scpsys_domain_data_mt8188,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188),
};
#endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */

146
drivers/soc/mediatek/mt8195-mmsys.h
View File

@ -75,6 +75,77 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
#define MT8195_VDO1_HDR_TOP_CFG 0xd00
#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2
#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3
#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
#define MT8195_SOUT_TO_MIXER_IN1_SEL 1
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
#define MT8195_SOUT_TO_MIXER_IN2_SEL 1
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
#define MT8195_SOUT_TO_MIXER_IN3_SEL 1
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
#define MT8195_SOUT_TO_MIXER_IN4_SEL 1
#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0
#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0
#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0
#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@ -367,4 +438,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
{
DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
}, {
DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
}, {
DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
}, {
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN1_SEL
}, {
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN2_SEL
}, {
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN3_SEL
}, {
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN4_SEL
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
}, {
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DPI1_SEL
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */

11
drivers/soc/mediatek/mtk-devapc.c
View File

@ -276,19 +276,14 @@ static int mtk_devapc_probe(struct platform_device *pdev)
if (!devapc_irq)
return -EINVAL;
ctx->infra_clk = devm_clk_get(&pdev->dev, "devapc-infra-clock");
ctx->infra_clk = devm_clk_get_enabled(&pdev->dev, "devapc-infra-clock");
if (IS_ERR(ctx->infra_clk))
return -EINVAL;
if (clk_prepare_enable(ctx->infra_clk))
return -EINVAL;
ret = devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq,
IRQF_TRIGGER_NONE, "devapc", ctx);
if (ret) {
clk_disable_unprepare(ctx->infra_clk);
if (ret)
return ret;
}
platform_set_drvdata(pdev, ctx);
@ -303,8 +298,6 @@ static int mtk_devapc_remove(struct platform_device *pdev)
stop_devapc(ctx);
clk_disable_unprepare(ctx->infra_clk);
return 0;
}

202
drivers/soc/mediatek/mtk-mmsys.c
View File

@ -7,6 +7,7 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
@ -16,10 +17,13 @@
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8188-mmsys.h"
#include "mt8192-mmsys.h"
#include "mt8195-mmsys.h"
#include "mt8365-mmsys.h"
#define MMSYS_SW_RESET_PER_REG 32
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@ -51,6 +55,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
.num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@ -58,6 +63,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
.num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@ -65,6 +71,13 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.routes = mmsys_mt8186_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
.num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.clk_driver = "clk-mt8188-vdo0",
.routes = mmsys_mt8188_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@ -72,6 +85,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.routes = mmsys_mt8192_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
.num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
@ -80,6 +94,24 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_vdo1_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
.sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
.num_resets = 64,
};
static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
.clk_driver = "clk-mt8195-vpp0",
.is_vppsys = true,
};
static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
.clk_driver = "clk-mt8195-vpp1",
.is_vppsys = true,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@ -91,24 +123,44 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
struct cmdq_client_reg cmdq_base;
};
static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,
struct cmdq_pkt *cmdq_pkt)
{
u32 tmp;
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (cmdq_pkt) {
if (mmsys->cmdq_base.size == 0) {
pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq");
return;
}
cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
mmsys->cmdq_base.offset + offset, val,
mask);
return;
}
#endif
tmp = readl_relaxed(mmsys->regs + offset);
tmp = (tmp & ~mask) | (val & mask);
writel_relaxed(tmp, mmsys->regs + offset);
}
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
u32 reg;
int i;
for (i = 0; i < mmsys->data->num_routes; i++)
if (cur == routes[i].from_comp && next == routes[i].to_comp) {
reg = readl_relaxed(mmsys->regs + routes[i].addr);
reg &= ~routes[i].mask;
reg |= routes[i].val;
writel_relaxed(reg, mmsys->regs + routes[i].addr);
}
if (cur == routes[i].from_comp && next == routes[i].to_comp)
mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
routes[i].val, NULL);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@ -118,26 +170,51 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
u32 reg;
int i;
for (i = 0; i < mmsys->data->num_routes; i++)
if (cur == routes[i].from_comp && next == routes[i].to_comp) {
reg = readl_relaxed(mmsys->regs + routes[i].addr);
reg &= ~routes[i].mask;
writel_relaxed(reg, mmsys->regs + routes[i].addr);
}
if (cur == routes[i].from_comp && next == routes[i].to_comp)
mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height,
struct cmdq_pkt *cmdq_pkt)
{
u32 tmp;
tmp = readl_relaxed(mmsys->regs + offset);
tmp = (tmp & ~mask) | val;
writel_relaxed(tmp, mmsys->regs + offset);
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
~0, height << 16 | width, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
struct cmdq_pkt *cmdq_pkt)
{
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
be_height << 16 | be_width, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
alpha << 16 | alpha, cmdq_pkt);
mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
alpha_sel << (19 + idx), cmdq_pkt);
mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
struct cmdq_pkt *cmdq_pkt)
{
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
BIT(4), channel_swap << 4, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
@ -146,20 +223,20 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
switch (val) {
case MTK_DPI_RGB888_SDR_CON:
mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON);
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL);
break;
case MTK_DPI_RGB565_SDR_CON:
mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON);
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL);
break;
case MTK_DPI_RGB565_DDR_CON:
mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON);
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL);
break;
case MTK_DPI_RGB888_DDR_CON:
default:
mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON);
MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL);
break;
}
}
@ -170,18 +247,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
{
struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
unsigned long flags;
u32 offset;
u32 reg;
offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
id = id % MMSYS_SW_RESET_PER_REG;
reg = mmsys->data->sw0_rst_offset + offset;
spin_lock_irqsave(&mmsys->lock, flags);
reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
if (assert)
reg &= ~BIT(id);
mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL);
else
reg |= BIT(id);
writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL);
spin_unlock_irqrestore(&mmsys->lock, flags);
@ -236,19 +314,28 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
spin_lock_init(&mmsys->lock);
mmsys->data = of_device_get_match_data(&pdev->dev);
mmsys->rcdev.owner = THIS_MODULE;
mmsys->rcdev.nr_resets = 32;
mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
mmsys->rcdev.of_node = pdev->dev.of_node;
ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
if (ret) {
dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
return ret;
if (mmsys->data->num_resets > 0) {
spin_lock_init(&mmsys->lock);
mmsys->rcdev.owner = THIS_MODULE;
mmsys->rcdev.nr_resets = mmsys->data->num_resets;
mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
mmsys->rcdev.of_node = pdev->dev.of_node;
ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
if (ret) {
dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
return ret;
}
}
mmsys->data = of_device_get_match_data(&pdev->dev);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
if (ret)
dev_dbg(dev, "No mediatek,gce-client-reg!\n");
#endif
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@ -256,6 +343,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
if (IS_ERR(clks))
return PTR_ERR(clks);
if (mmsys->data->is_vppsys)
goto out_probe_done;
drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(drm)) {
@ -263,6 +353,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return PTR_ERR(drm);
}
out_probe_done:
return 0;
}
@ -299,6 +390,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8186-mmsys",
.data = &mt8186_mmsys_driver_data,
},
{
.compatible = "mediatek,mt8188-vdosys0",
.data = &mt8188_vdosys0_driver_data,
},
{
.compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data,
@ -311,6 +406,18 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
{
.compatible = "mediatek,mt8195-vdosys1",
.data = &mt8195_vdosys1_driver_data,
},
{
.compatible = "mediatek,mt8195-vppsys0",
.data = &mt8195_vppsys0_driver_data,
},
{
.compatible = "mediatek,mt8195-vppsys1",
.data = &mt8195_vppsys1_driver_data,
},
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
@ -326,4 +433,19 @@ static struct platform_driver mtk_mmsys_drv = {
.probe = mtk_mmsys_probe,
};
builtin_platform_driver(mtk_mmsys_drv);
static int __init mtk_mmsys_init(void)
{
return platform_driver_register(&mtk_mmsys_drv);
}
static void __exit mtk_mmsys_exit(void)
{
platform_driver_unregister(&mtk_mmsys_drv);
}
module_init(mtk_mmsys_init);
module_exit(mtk_mmsys_exit);
MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek SoC MMSYS driver");
MODULE_LICENSE("GPL");

2
drivers/soc/mediatek/mtk-mmsys.h
View File

@ -91,6 +91,8 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
const u32 num_resets;
const bool is_vppsys;
};
/*

113
drivers/soc/mediatek/mtk-mutex.c
View File

@ -116,6 +116,21 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
#define MT8188_MUTEX_MOD_DISP_OVL0 0
#define MT8188_MUTEX_MOD_DISP_WDMA0 1
#define MT8188_MUTEX_MOD_DISP_RDMA0 2
#define MT8188_MUTEX_MOD_DISP_COLOR0 3
#define MT8188_MUTEX_MOD_DISP_CCORR0 4
#define MT8188_MUTEX_MOD_DISP_AAL0 5
#define MT8188_MUTEX_MOD_DISP_GAMMA0 6
#define MT8188_MUTEX_MOD_DISP_DITHER0 7
#define MT8188_MUTEX_MOD_DISP_DSI0 8
#define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
#define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20
#define MT8188_MUTEX_MOD_DISP_DP_INTF0 21
#define MT8188_MUTEX_MOD_DISP_POSTMASK0 24
#define MT8188_MUTEX_MOD2_DISP_PWM0 33
#define MT8195_MUTEX_MOD_DISP_OVL0 0
#define MT8195_MUTEX_MOD_DISP_WDMA0 1
#define MT8195_MUTEX_MOD_DISP_RDMA0 2
@ -130,6 +145,24 @@
#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
#define MT8195_MUTEX_MOD_DISP_PWM0 27
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6
#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7
#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8
#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9
#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10
#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11
#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12
#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18
#define MT8195_MUTEX_MOD_DISP1_DPI0 25
#define MT8195_MUTEX_MOD_DISP1_DPI1 26
#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27
#define MT8365_MUTEX_MOD_DISP_OVL0 7
#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
#define MT8365_MUTEX_MOD_DISP_RDMA0 9
@ -180,6 +213,8 @@
#define MT8167_MUTEX_SOF_DPI1 3
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
#define MT8188_MUTEX_SOF_DSI0 1
#define MT8188_MUTEX_SOF_DP_INTF0 3
#define MT8195_MUTEX_SOF_DSI0 1
#define MT8195_MUTEX_SOF_DSI1 2
#define MT8195_MUTEX_SOF_DP_INTF0 3
@ -189,6 +224,8 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
#define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
#define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
@ -344,6 +381,23 @@ static const unsigned int mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
[MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0,
};
static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0,
[DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0,
[DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE,
[DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
};
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
@ -372,6 +426,21 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
[DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0,
[DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1,
[DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2,
[DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3,
[DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4,
[DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5,
[DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6,
[DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7,
[DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0,
[DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1,
[DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2,
[DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
[DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
[DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
[DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@ -435,6 +504,14 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
* but also detect the error at end of frame(EAEOF) when EOF signal
* arrives.
*/
static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] =
MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
[MUTEX_SOF_DP_INTF0] =
MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
};
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
@ -505,6 +582,13 @@ static const struct mtk_mutex_data mt8186_mutex_driver_data = {
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
static const struct mtk_mutex_data mt8188_mutex_driver_data = {
.mutex_mod = mt8188_mutex_mod,
.mutex_sof = mt8188_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_mod = mt8192_mutex_mod,
.mutex_sof = mt8183_mutex_sof,
@ -602,6 +686,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
case DDP_COMPONENT_DP_INTF1:
sof_id = MUTEX_SOF_DP_INTF1;
break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@ -642,6 +729,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@ -832,11 +920,6 @@ static int mtk_mutex_probe(struct platform_device *pdev)
return 0;
}
static int mtk_mutex_remove(struct platform_device *pdev)
{
return 0;
}
static const struct of_device_id mutex_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = &mt2701_mutex_driver_data},
@ -854,6 +937,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8186-mdp3-mutex",
.data = &mt8186_mdp_mutex_driver_data},
{ .compatible = "mediatek,mt8188-disp-mutex",
.data = &mt8188_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
{ .compatible = "mediatek,mt8195-disp-mutex",
@ -866,7 +951,6 @@ MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
static struct platform_driver mtk_mutex_driver = {
.probe = mtk_mutex_probe,
.remove = mtk_mutex_remove,
.driver = {
.name = "mediatek-mutex",
.owner = THIS_MODULE,
@ -874,4 +958,19 @@ static struct platform_driver mtk_mutex_driver = {
},
};
builtin_platform_driver(mtk_mutex_driver);
static int __init mtk_mutex_init(void)
{
return platform_driver_register(&mtk_mutex_driver);
}
static void __exit mtk_mutex_exit(void)
{
platform_driver_unregister(&mtk_mutex_driver);
}
module_init(mtk_mutex_init);
module_exit(mtk_mutex_exit);
MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek SoC MUTEX driver");
MODULE_LICENSE("GPL");

13
drivers/soc/mediatek/mtk-pm-domains.c
View File

@ -21,6 +21,7 @@
#include "mt8173-pm-domains.h"
#include "mt8183-pm-domains.h"
#include "mt8186-pm-domains.h"
#include "mt8188-pm-domains.h"
#include "mt8192-pm-domains.h"
#include "mt8195-pm-domains.h"
@ -218,6 +219,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret)
goto err_reg;
if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO))
regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs,
pd->data->ext_buck_iso_mask);
/* subsys power on */
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
@ -272,6 +277,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
return ret;
if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO))
regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs,
pd->data->ext_buck_iso_mask);
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
/* subsys power off */
@ -579,6 +588,10 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt8186-power-controller",
.data = &mt8186_scpsys_data,
},
{
.compatible = "mediatek,mt8188-power-controller",
.data = &mt8188_scpsys_data,
},
{
.compatible = "mediatek,mt8192-power-controller",
.data = &mt8192_scpsys_data,

5
drivers/soc/mediatek/mtk-pm-domains.h
View File

@ -10,6 +10,7 @@
#define MTK_SCPD_DOMAIN_SUPPLY BIT(4)
/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
#define MTK_SCPD_ALWAYS_ON BIT(5)
#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@ -81,6 +82,8 @@ struct scpsys_bus_prot_data {
* @ctl_offs: The offset for main power control register.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @ext_buck_iso_offs: The offset for external buck isolation
* @ext_buck_iso_mask: The mask for external buck isolation
* @caps: The flag for active wake-up action.
* @bp_infracfg: bus protection for infracfg subsystem
* @bp_smi: bus protection for smi subsystem
@ -91,6 +94,8 @@ struct scpsys_domain_data {
int ctl_offs;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
int ext_buck_iso_offs;
u32 ext_buck_iso_mask;
u8 caps;
const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];

159
drivers/soc/mediatek/mtk-regulator-coupler.c Normal file
View File

@ -0,0 +1,159 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Voltage regulators coupler for MediaTek SoCs
*
* Copyright (C) 2022 Collabora, Ltd.
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/regulator/coupler.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/suspend.h>
#define to_mediatek_coupler(x) container_of(x, struct mediatek_regulator_coupler, coupler)
struct mediatek_regulator_coupler {
struct regulator_coupler coupler;
struct regulator_dev *vsram_rdev;
};
/*
* We currently support only couples of not more than two vregs and
* modify the vsram voltage only when changing voltage of vgpu.
*
* This function is limited to the GPU<->SRAM voltages relationships.
*/
static int mediatek_regulator_balance_voltage(struct regulator_coupler *coupler,
struct regulator_dev *rdev,
suspend_state_t state)
{
struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler);
int max_spread = rdev->constraints->max_spread[0];
int vsram_min_uV = mrc->vsram_rdev->constraints->min_uV;
int vsram_max_uV = mrc->vsram_rdev->constraints->max_uV;
int vsram_target_min_uV, vsram_target_max_uV;
int min_uV = 0;
int max_uV = INT_MAX;
int ret;
/*
* If the target device is on, setting the SRAM voltage directly
* is not supported as it scales through its coupled supply voltage.
*
* An exception is made in case the use_count is zero: this means
* that this is the first time we power up the SRAM regulator, which
* implies that the target device has yet to perform initialization
* and setting a voltage at that time is harmless.
*/
if (rdev == mrc->vsram_rdev) {
if (rdev->use_count == 0)
return regulator_do_balance_voltage(rdev, state, true);
return -EPERM;
}
ret = regulator_check_consumers(rdev, &min_uV, &max_uV, state);
if (ret < 0)
return ret;
if (min_uV == 0) {
ret = regulator_get_voltage_rdev(rdev);
if (ret < 0)
return ret;
min_uV = ret;
}
ret = regulator_check_voltage(rdev, &min_uV, &max_uV);
if (ret < 0)
return ret;
/*
* If we're asked to set a voltage less than VSRAM min_uV, set
* the minimum allowed voltage on VSRAM, as in this case it is
* safe to ignore the max_spread parameter.
*/
vsram_target_min_uV = max(vsram_min_uV, min_uV + max_spread);
vsram_target_max_uV = min(vsram_max_uV, vsram_target_min_uV + max_spread);
/* Make sure we're not out of range */
vsram_target_min_uV = min(vsram_target_min_uV, vsram_max_uV);
pr_debug("Setting voltage %d-%duV on %s (minuV %d)\n",
vsram_target_min_uV, vsram_target_max_uV,
rdev_get_name(mrc->vsram_rdev), min_uV);
ret = regulator_set_voltage_rdev(mrc->vsram_rdev, vsram_target_min_uV,
vsram_target_max_uV, state);
if (ret)
return ret;
/* The sram voltage is now balanced: update the target vreg voltage */
return regulator_do_balance_voltage(rdev, state, true);
}
static int mediatek_regulator_attach(struct regulator_coupler *coupler,
struct regulator_dev *rdev)
{
struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler);
const char *rdev_name = rdev_get_name(rdev);
/*
* If we're getting a coupling of more than two regulators here and
* this means that this is surely not a GPU<->SRAM couple: in that
* case, we may want to use another coupler implementation, if any,
* or the generic one: the regulator core will keep walking through
* the list of couplers when any .attach_regulator() cb returns 1.
*/
if (rdev->coupling_desc.n_coupled > 2)
return 1;
if (strstr(rdev_name, "sram")) {
if (mrc->vsram_rdev)
return -EINVAL;
mrc->vsram_rdev = rdev;
} else if (!strstr(rdev_name, "vgpu") && !strstr(rdev_name, "Vgpu")) {
return 1;
}
return 0;
}
static int mediatek_regulator_detach(struct regulator_coupler *coupler,
struct regulator_dev *rdev)
{
struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler);
if (rdev == mrc->vsram_rdev)
mrc->vsram_rdev = NULL;
return 0;
}
static struct mediatek_regulator_coupler mediatek_coupler = {
.coupler = {
.attach_regulator = mediatek_regulator_attach,
.detach_regulator = mediatek_regulator_detach,
.balance_voltage = mediatek_regulator_balance_voltage,
},
};
static int mediatek_regulator_coupler_init(void)
{
if (!of_machine_is_compatible("mediatek,mt8183") &&
!of_machine_is_compatible("mediatek,mt8186") &&
!of_machine_is_compatible("mediatek,mt8192"))
return 0;
return regulator_coupler_register(&mediatek_coupler.coupler);
}
arch_initcall(mediatek_regulator_coupler_init);
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
MODULE_DESCRIPTION("MediaTek Regulator Coupler driver");
MODULE_LICENSE("GPL");

177
drivers/soc/mediatek/mtk-svs.c
View File

@ -138,6 +138,7 @@
static DEFINE_SPINLOCK(svs_lock);
#ifdef CONFIG_DEBUG_FS
#define debug_fops_ro(name) \
static int svs_##name##_debug_open(struct inode *inode, \
struct file *filp) \
@ -170,6 +171,7 @@ static DEFINE_SPINLOCK(svs_lock);
}
#define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops}
#endif
/**
* enum svsb_phase - svs bank phase enumeration
@ -311,15 +313,12 @@ static const u32 svs_regs_v2[] = {
/**
* struct svs_platform - svs platform control
* @name: svs platform name
* @base: svs platform register base
* @dev: svs platform device
* @main_clk: main clock for svs bank
* @pbank: svs bank pointer needing to be protected by spin_lock section
* @banks: svs banks that svs platform supports
* @rst: svs platform reset control
* @efuse_parsing: svs platform efuse parsing function pointer
* @probe: svs platform probe function pointer
* @efuse_max: total number of svs efuse
* @tefuse_max: total number of thermal efuse
* @regs: svs platform registers map
@ -328,15 +327,12 @@ static const u32 svs_regs_v2[] = {
* @tefuse: thermal efuse data received from NVMEM framework
*/
struct svs_platform {
char *name;
void __iomem *base;
struct device *dev;
struct clk *main_clk;
struct svs_bank *pbank;
struct svs_bank *banks;
struct reset_control *rst;
bool (*efuse_parsing)(struct svs_platform *svsp);
int (*probe)(struct svs_platform *svsp);
size_t efuse_max;
size_t tefuse_max;
const u32 *regs;
@ -628,6 +624,7 @@ unlock_mutex:
return ret;
}
#ifdef CONFIG_DEBUG_FS
static int svs_dump_debug_show(struct seq_file *m, void *p)
{
struct svs_platform *svsp = (struct svs_platform *)m->private;
@ -843,6 +840,7 @@ static int svs_create_debug_cmds(struct svs_platform *svsp)
return 0;
}
#endif /* CONFIG_DEBUG_FS */
static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx)
{
@ -1324,7 +1322,7 @@ static int svs_init01(struct svs_platform *svsp)
svsb->pm_runtime_enabled_count++;
}
ret = pm_runtime_get_sync(svsb->opp_dev);
ret = pm_runtime_resume_and_get(svsb->opp_dev);
if (ret < 0) {
dev_err(svsb->dev, "mtcmos on fail: %d\n", ret);
goto svs_init01_resume_cpuidle;
@ -1461,6 +1459,7 @@ static int svs_init02(struct svs_platform *svsp)
{
struct svs_bank *svsb;
unsigned long flags, time_left;
int ret;
u32 idx;
for (idx = 0; idx < svsp->bank_max; idx++) {
@ -1479,7 +1478,8 @@ static int svs_init02(struct svs_platform *svsp)
msecs_to_jiffies(5000));
if (!time_left) {
dev_err(svsb->dev, "init02 completion timeout\n");
return -EBUSY;
ret = -EBUSY;
goto out_of_init02;
}
}
@ -1497,12 +1497,30 @@ static int svs_init02(struct svs_platform *svsp)
if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) {
if (svs_sync_bank_volts_from_opp(svsb)) {
dev_err(svsb->dev, "sync volt fail\n");
return -EPERM;
ret = -EPERM;
goto out_of_init02;
}
}
}
return 0;
out_of_init02:
for (idx = 0; idx < svsp->bank_max; idx++) {
svsb = &svsp->banks[idx];
spin_lock_irqsave(&svs_lock, flags);
svsp->pbank = svsb;
svs_switch_bank(svsp);
svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
spin_unlock_irqrestore(&svs_lock, flags);
svsb->phase = SVSB_PHASE_ERROR;
svs_adjust_pm_opp_volts(svsb);
}
return ret;
}
static void svs_mon_mode(struct svs_platform *svsp)
@ -1594,12 +1612,16 @@ static int svs_resume(struct device *dev)
ret = svs_init02(svsp);
if (ret)
goto out_of_resume;
goto svs_resume_reset_assert;
svs_mon_mode(svsp);
return 0;
svs_resume_reset_assert:
dev_err(svsp->dev, "assert reset: %d\n",
reset_control_assert(svsp->rst));
out_of_resume:
clk_disable_unprepare(svsp->main_clk);
return ret;
@ -1899,26 +1921,27 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
if (adc_cali_en_t == 1) {
if (!ts_id)
o_slope = 0;
if (adc_ge_t < 265 || adc_ge_t > 758 ||
adc_oe_t < 265 || adc_oe_t > 758 ||
o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
o_vtsabb < -8 || o_vtsabb > 484 ||
degc_cali < 1 || degc_cali > 63) {
dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
goto remove_mt8183_svsb_mon_mode;
}
if (!ts_id) {
o_slope = 1534;
} else {
dev_err(svsp->dev, "no thermal efuse, no mon mode\n");
o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
if (!o_slope_sign)
o_slope = 1534 + o_slope * 10;
else
o_slope = 1534 - o_slope * 10;
}
if (adc_cali_en_t == 0 ||
adc_ge_t < 265 || adc_ge_t > 758 ||
adc_oe_t < 265 || adc_oe_t > 758 ||
o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
o_vtsabb < -8 || o_vtsabb > 484 ||
degc_cali < 1 || degc_cali > 63) {
dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
goto remove_mt8183_svsb_mon_mode;
}
@ -1937,11 +1960,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain;
temp0 = (10000 * 100000 / gain) * 15 / 18;
if (!o_slope_sign)
mts = (temp0 * 10) / (1534 + o_slope * 10);
else
mts = (temp0 * 10) / (1534 - o_slope * 10);
mts = (temp0 * 10) / o_slope;
for (idx = 0; idx < svsp->bank_max; idx++) {
svsb = &svsp->banks[idx];
@ -1968,11 +1987,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
temp0 = (degc_cali * 10 / 2);
temp1 = ((10000 * 100000 / 4096 / gain) *
oe + tb_roomt * 10) * 15 / 18;
if (!o_slope_sign)
temp2 = temp1 * 100 / (1534 + o_slope * 10);
else
temp2 = temp1 * 100 / (1534 - o_slope * 10);
temp2 = temp1 * 100 / o_slope;
svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
}
@ -2011,7 +2026,7 @@ static bool svs_is_efuse_data_correct(struct svs_platform *svsp)
svsp->efuse_max /= sizeof(u32);
nvmem_cell_put(cell);
return svsp->efuse_parsing(svsp);
return true;
}
static struct device *svs_get_subsys_device(struct svs_platform *svsp,
@ -2326,50 +2341,38 @@ static const struct of_device_id svs_of_match[] = {
/* Sentinel */
},
};
static struct svs_platform *svs_platform_probe(struct platform_device *pdev)
{
struct svs_platform *svsp;
const struct svs_platform_data *svsp_data;
int ret;
svsp_data = of_device_get_match_data(&pdev->dev);
if (!svsp_data) {
dev_err(&pdev->dev, "no svs platform data?\n");
return ERR_PTR(-EPERM);
}
svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
if (!svsp)
return ERR_PTR(-ENOMEM);
svsp->dev = &pdev->dev;
svsp->name = svsp_data->name;
svsp->banks = svsp_data->banks;
svsp->efuse_parsing = svsp_data->efuse_parsing;
svsp->probe = svsp_data->probe;
svsp->regs = svsp_data->regs;
svsp->bank_max = svsp_data->bank_max;
ret = svsp->probe(svsp);
if (ret)
return ERR_PTR(ret);
return svsp;
}
MODULE_DEVICE_TABLE(of, svs_of_match);
static int svs_probe(struct platform_device *pdev)
{
struct svs_platform *svsp;
int svsp_irq, ret;
const struct svs_platform_data *svsp_data;
int ret, svsp_irq;
svsp = svs_platform_probe(pdev);
if (IS_ERR(svsp))
return PTR_ERR(svsp);
svsp_data = of_device_get_match_data(&pdev->dev);
svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
if (!svsp)
return -ENOMEM;
svsp->dev = &pdev->dev;
svsp->banks = svsp_data->banks;
svsp->regs = svsp_data->regs;
svsp->bank_max = svsp_data->bank_max;
ret = svsp_data->probe(svsp);
if (ret)
return ret;
if (!svs_is_efuse_data_correct(svsp)) {
dev_notice(svsp->dev, "efuse data isn't correct\n");
ret = -EPERM;
goto svs_probe_free_efuse;
}
if (!svsp_data->efuse_parsing(svsp)) {
dev_err(svsp->dev, "efuse data parsing failed\n");
ret = -EPERM;
goto svs_probe_free_resource;
}
@ -2385,14 +2388,6 @@ static int svs_probe(struct platform_device *pdev)
goto svs_probe_free_resource;
}
ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
IRQF_ONESHOT, svsp->name, svsp);
if (ret) {
dev_err(svsp->dev, "register irq(%d) failed: %d\n",
svsp_irq, ret);
goto svs_probe_free_resource;
}
svsp->main_clk = devm_clk_get(svsp->dev, "main");
if (IS_ERR(svsp->main_clk)) {
dev_err(svsp->dev, "failed to get clock: %ld\n",
@ -2414,17 +2409,27 @@ static int svs_probe(struct platform_device *pdev)
goto svs_probe_clk_disable;
}
ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
IRQF_ONESHOT, svsp_data->name, svsp);
if (ret) {
dev_err(svsp->dev, "register irq(%d) failed: %d\n",
svsp_irq, ret);
goto svs_probe_iounmap;
}
ret = svs_start(svsp);
if (ret) {
dev_err(svsp->dev, "svs start fail: %d\n", ret);
goto svs_probe_iounmap;
}
#ifdef CONFIG_DEBUG_FS
ret = svs_create_debug_cmds(svsp);
if (ret) {
dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret);
goto svs_probe_iounmap;
}
#endif
return 0;
@ -2435,11 +2440,13 @@ svs_probe_clk_disable:
clk_disable_unprepare(svsp->main_clk);
svs_probe_free_resource:
if (!IS_ERR_OR_NULL(svsp->efuse))
kfree(svsp->efuse);
if (!IS_ERR_OR_NULL(svsp->tefuse))
kfree(svsp->tefuse);
svs_probe_free_efuse:
if (!IS_ERR_OR_NULL(svsp->efuse))
kfree(svsp->efuse);
return ret;
}

44
include/dt-bindings/power/mediatek,mt8188-power.h Normal file
View File

@ -0,0 +1,44 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <garmin.chang@mediatek.com>
*/
#ifndef _DT_BINDINGS_POWER_MT8188_POWER_H
#define _DT_BINDINGS_POWER_MT8188_POWER_H
#define MT8188_POWER_DOMAIN_MFG0 0
#define MT8188_POWER_DOMAIN_MFG1 1
#define MT8188_POWER_DOMAIN_MFG2 2
#define MT8188_POWER_DOMAIN_MFG3 3
#define MT8188_POWER_DOMAIN_MFG4 4
#define MT8188_POWER_DOMAIN_PEXTP_MAC_P0 5
#define MT8188_POWER_DOMAIN_PEXTP_PHY_TOP 6
#define MT8188_POWER_DOMAIN_CSIRX_TOP 7
#define MT8188_POWER_DOMAIN_ETHER 8
#define MT8188_POWER_DOMAIN_HDMI_TX 9
#define MT8188_POWER_DOMAIN_ADSP_AO 10
#define MT8188_POWER_DOMAIN_ADSP_INFRA 11
#define MT8188_POWER_DOMAIN_ADSP 12
#define MT8188_POWER_DOMAIN_AUDIO 13
#define MT8188_POWER_DOMAIN_AUDIO_ASRC 14
#define MT8188_POWER_DOMAIN_VPPSYS0 15
#define MT8188_POWER_DOMAIN_VDOSYS0 16
#define MT8188_POWER_DOMAIN_VDOSYS1 17
#define MT8188_POWER_DOMAIN_DP_TX 18
#define MT8188_POWER_DOMAIN_EDP_TX 19
#define MT8188_POWER_DOMAIN_VPPSYS1 20
#define MT8188_POWER_DOMAIN_WPE 21
#define MT8188_POWER_DOMAIN_VDEC0 22
#define MT8188_POWER_DOMAIN_VDEC1 23
#define MT8188_POWER_DOMAIN_VENC 24
#define MT8188_POWER_DOMAIN_IMG_VCORE 25
#define MT8188_POWER_DOMAIN_IMG_MAIN 26
#define MT8188_POWER_DOMAIN_DIP 27
#define MT8188_POWER_DOMAIN_IPE 28
#define MT8188_POWER_DOMAIN_CAM_VCORE 29
#define MT8188_POWER_DOMAIN_CAM_MAIN 30
#define MT8188_POWER_DOMAIN_CAM_SUBA 31
#define MT8188_POWER_DOMAIN_CAM_SUBB 32
#endif /* _DT_BINDINGS_POWER_MT8188_POWER_H */

45
include/dt-bindings/reset/mt8195-resets.h
View File

@ -35,4 +35,49 @@
#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4
#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5
/* VDOSYS1 */
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1
#define MT8195_VDOSYS1_SW0_RST_B_GALS 2
#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3
#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13
#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14
#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15
#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20
#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21
#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22
#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23
#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24
#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30
#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49
#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */

121
include/linux/soc/mediatek/infracfg.h
View File

@ -140,6 +140,127 @@
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
#define MT8188_TOP_AXI_PROT_EN_SET 0x2A0
#define MT8188_TOP_AXI_PROT_EN_CLR 0x2A4
#define MT8188_TOP_AXI_PROT_EN_STA 0x228
#define MT8188_TOP_AXI_PROT_EN_1_SET 0x2A8
#define MT8188_TOP_AXI_PROT_EN_1_CLR 0x2AC
#define MT8188_TOP_AXI_PROT_EN_1_STA 0x258
#define MT8188_TOP_AXI_PROT_EN_2_SET 0x714
#define MT8188_TOP_AXI_PROT_EN_2_CLR 0x718
#define MT8188_TOP_AXI_PROT_EN_2_STA 0x724
#define MT8188_TOP_AXI_PROT_EN_MM_SET 0x2D4
#define MT8188_TOP_AXI_PROT_EN_MM_CLR 0x2D8
#define MT8188_TOP_AXI_PROT_EN_MM_STA 0x2EC
#define MT8188_TOP_AXI_PROT_EN_MM_2_SET 0xDCC
#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR 0xDD0
#define MT8188_TOP_AXI_PROT_EN_MM_2_STA 0xDD8
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET 0xB84
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR 0xB88
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA 0xB90
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xBCC
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xBD0
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA 0xBD8
#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 BIT(11)
#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 BIT(7)
#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 BIT(19)
#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(5)
#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 GENMASK(22, 21)
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 BIT(17)
#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 BIT(2)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30))
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1 BIT(24)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1 BIT(20)
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 GENMASK(31, 29)
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28))
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \
BIT(27))
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25))
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 GENMASK(11, 8)
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 GENMASK(22, 21)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 BIT(20)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 BIT(12)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 BIT(24)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 BIT(13)
#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 BIT(10)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 GENMASK(9, 8)
#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11))
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20))
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20))
#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 BIT(6)
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 BIT(21)
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 GENMASK(31, 30)
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2 BIT(22)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 BIT(10)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1 BIT(22)
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 GENMASK(6, 5)
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 BIT(18)
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2 BIT(21)
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(13)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(13)
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(14)
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(29)
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9) | BIT(11))
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 BIT(26)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3 BIT(2)
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1) | BIT(3))
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 BIT(25)
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 BIT(16)
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 GENMASK(27, 26)
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 GENMASK(25, 24)
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2) | BIT(4))
#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 BIT(0)
#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 BIT(22)
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 BIT(24)
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 BIT(17)
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 GENMASK(31, 30)
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2 BIT(2)
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 GENMASK(29, 28)
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4 BIT(1)
#define MT8188_SMI_COMMON_CLAMP_EN_STA 0x3C0
#define MT8188_SMI_COMMON_CLAMP_EN_SET 0x3C4
#define MT8188_SMI_COMMON_CLAMP_EN_CLR 0x3C8
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 GENMASK(3, 1)
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 GENMASK(2, 1)
#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 BIT(0)
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 GENMASK(3, 2)
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 GENMASK(3, 2)
#define MT8188_SMI_LARB10_RESET_ADDR 0xC
#define MT8188_SMI_LARB11A_RESET_ADDR 0xC
#define MT8188_SMI_LARB11C_RESET_ADDR 0xC
#define MT8188_SMI_LARB12_RESET_ADDR 0xC
#define MT8188_SMI_LARB11B_RESET_ADDR 0xC
#define MT8188_SMI_LARB15_RESET_ADDR 0xC
#define MT8188_SMI_LARB16B_RESET_ADDR 0xA0
#define MT8188_SMI_LARB17B_RESET_ADDR 0xA0
#define MT8188_SMI_LARB16A_RESET_ADDR 0xA0
#define MT8188_SMI_LARB17A_RESET_ADDR 0xA0
#define MT8188_SMI_LARB10_RESET BIT(0)
#define MT8188_SMI_LARB11A_RESET BIT(0)
#define MT8188_SMI_LARB11C_RESET BIT(0)
#define MT8188_SMI_LARB12_RESET BIT(8)
#define MT8188_SMI_LARB11B_RESET BIT(0)
#define MT8188_SMI_LARB15_RESET BIT(0)
#define MT8188_SMI_LARB16B_RESET BIT(4)
#define MT8188_SMI_LARB17B_RESET BIT(4)
#define MT8188_SMI_LARB16A_RESET BIT(4)
#define MT8188_SMI_LARB17A_RESET BIT(4)
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)

25
include/linux/soc/mediatek/mtk-mmsys.h
View File

@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
#include <linux/mailbox_controller.h>
#include <linux/mailbox/mtk-cmdq-mailbox.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
enum mtk_ddp_comp_id;
struct device;
@ -36,7 +40,16 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_ETHDR_MIXER,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_MDP_RDMA0,
DDP_COMPONENT_MDP_RDMA1,
DDP_COMPONENT_MDP_RDMA2,
DDP_COMPONENT_MDP_RDMA3,
DDP_COMPONENT_MDP_RDMA4,
DDP_COMPONENT_MDP_RDMA5,
DDP_COMPONENT_MDP_RDMA6,
DDP_COMPONENT_MDP_RDMA7,
DDP_COMPONENT_MERGE0,
DDP_COMPONENT_MERGE1,
DDP_COMPONENT_MERGE2,
@ -74,4 +87,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width,
int height, struct cmdq_pkt *cmdq_pkt);
void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
struct cmdq_pkt *cmdq_pkt);
void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);
void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */