drm/i915/gt: Sanitize GT first
We see that if the HW doesn't actually sleep, the HW may eat the poison we set in its write-only HWSP during sanitize: intel_gt_resume.part.8: 0000:00:02.0 __gt_unpark: 0000:00:02.0 gt_sanitize: 0000:00:02.0 force:yes process_csb: 0000:00:02.0 vcs0: cs-irq head=5, tail=90 process_csb: 0000:00:02.0 vcs0: csb[0]: status=0x5a5a5a5a:0x5a5a5a5a assert_pending_valid: Nothing pending for promotion! The CS TAIL pointer should have been reset by reset_csb_pointers(), so in this case it is likely that we have read back from the CPU cache and so we must clflush our control over that page. In doing so, push the sanitisation to the start of the GT sequence so that our poisoning is assuredly before we start talking to the HW. References: https://gitlab.freedesktop.org/drm/intel/-/issues/1794 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200427084000.10999-1-chris@chris-wilson.co.uk
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@ -198,11 +198,12 @@ int intel_gt_resume(struct intel_gt *gt)
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* Only the kernel contexts should remain pinned over suspend,
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* allowing us to fixup the user contexts on their first pin.
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*/
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gt_sanitize(gt, true);
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intel_gt_pm_get(gt);
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intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
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intel_rc6_sanitize(>->rc6);
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gt_sanitize(gt, true);
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if (intel_gt_is_wedged(gt)) {
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err = -EIO;
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goto out_fw;
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@ -3931,6 +3931,9 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
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* reset the value in the HWSP.
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*/
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intel_timeline_reset_seqno(engine->kernel_context->timeline);
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/* And scrub the dirty cachelines for the HWSP */
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clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
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}
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static void enable_error_interrupt(struct intel_engine_cs *engine)
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