media: dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192
Adds decoder dt-bindings for mt8192. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Yunfei Dong
Mauro Carvalho Chehab
parent
9cdd70ceb6
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Mediatek Video Decode Accelerator With Multi Hardware
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maintainers:
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- Yunfei Dong <yunfei.dong@mediatek.com>
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description: |
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Mediatek Video Decode is the video decode hardware present in Mediatek
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SoCs which supports high resolution decoding functionalities. Required
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parent and child device node.
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About the Decoder Hardware Block Diagram, please check below:
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+---------------------------------+------------------------------------+
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| | |
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| input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
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+------------||-------------------+---------------------||-------------+
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lat workqueue | core workqueue <parent>
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-------------||-----------------------------------------||------------------
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|| || <child>
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\/ <----------------HW index-------------->\/
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+------------------------------------------------------+
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| enable/disable |
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| clk power irq iommu |
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| (lat/lat soc/core0/core1) |
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+------------------------------------------------------+
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As above, there are parent and child devices, child mean each hardware. The child device
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controls the information of each hardware independent which include clk/power/irq.
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There are two workqueues in parent device: lat workqueue and core workqueue. They are used
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to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
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then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
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done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
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writing the result to output buffer, disable hardware when core decode done. These two
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hardwares will decode each frame cyclically.
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For the smi common may not the same for each hardware, can't combine all hardware in one node,
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or leading to iommu fault when access dram data.
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properties:
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compatible:
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const: mediatek,mt8192-vcodec-dec
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reg:
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maxItems: 1
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iommus:
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minItems: 1
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maxItems: 32
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description: |
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List of the hardware port in respective IOMMU block for current Socs.
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Refer to bindings/iommu/mediatek,iommu.yaml.
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mediatek,scp:
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$ref: /schemas/types.yaml#/definitions/phandle
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maxItems: 1
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description: |
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The node of system control processor (SCP), using
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the remoteproc & rpmsg framework.
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dma-ranges:
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maxItems: 1
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description: |
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Describes the physical address space of IOMMU maps to memory.
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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# Required child node:
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patternProperties:
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'^vcodec-lat@[0-9a-f]+$':
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type: object
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properties:
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compatible:
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const: mediatek,mtk-vcodec-lat
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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iommus:
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minItems: 1
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maxItems: 32
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description: |
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List of the hardware port in respective IOMMU block for current Socs.
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Refer to bindings/iommu/mediatek,iommu.yaml.
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clocks:
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maxItems: 5
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clock-names:
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items:
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- const: sel
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- const: soc-vdec
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- const: soc-lat
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- const: vdec
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- const: top
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- iommus
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- clocks
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- clock-names
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- assigned-clocks
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- assigned-clock-parents
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- power-domains
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additionalProperties: false
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'^vcodec-core@[0-9a-f]+$':
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type: object
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properties:
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compatible:
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const: mediatek,mtk-vcodec-core
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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iommus:
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minItems: 1
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maxItems: 32
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description: |
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List of the hardware port in respective IOMMU block for current Socs.
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Refer to bindings/iommu/mediatek,iommu.yaml.
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clocks:
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maxItems: 5
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clock-names:
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items:
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- const: sel
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- const: soc-vdec
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- const: soc-lat
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- const: vdec
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- const: top
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- iommus
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- clocks
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- clock-names
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- assigned-clocks
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- assigned-clock-parents
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- power-domains
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additionalProperties: false
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required:
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- compatible
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- reg
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- iommus
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- mediatek,scp
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- dma-ranges
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/mt8192-larb-port.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/mt8192-clk.h>
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#include <dt-bindings/power/mt8192-power.h>
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video-codec@16000000 {
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compatible = "mediatek,mt8192-vcodec-dec";
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mediatek,scp = <&scp>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
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dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x16000000 0x40000>;
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reg = <0x16000000 0x1000>; /* VDEC_SYS */
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vcodec-lat@10000 {
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compatible = "mediatek,mtk-vcodec-lat";
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reg = <0x10000 0x800>;
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interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
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<&vdecsys_soc CLK_VDEC_SOC_LAT>,
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<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
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};
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vcodec-core@25000 {
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compatible = "mediatek,mtk-vcodec-core";
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reg = <0x25000 0x1000>;
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interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys CLK_VDEC_VDEC>,
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<&vdecsys CLK_VDEC_LAT>,
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<&vdecsys CLK_VDEC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
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};
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};
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