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arm: Xilinx Zynq dt patches for v3.18 

- Add eth phys
 - Add led for zc702
 - Various dts cleanups
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.10 (GNU/Linux)
 
 iEYEABECAAYFAlQYFewACgkQykllyylKDCGHKgCeJK4b6TUOD3UNQgI8qu8UkUPV
 UQwAnRH5BSaqtTkiasx6feLE7dKpNHeW
 =Trb8
 -----END PGP SIGNATURE-----

Merge tag 'zynq-dt-for-3.18' of git://git.xilinx.com/linux-xlnx into next/dt

Pull "arm: Xilinx Zynq dt patches for v3.18" from Michal Simek:

- Add eth phys
- Add led for zc702
- Various dts cleanups

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* tag 'zynq-dt-for-3.18' of git://git.xilinx.com/linux-xlnx:
  ARM: zynq: Add ISL9305 regulator on Parallella board
  ARM: zynq: DT: Add Ethernet phys
  ARM: zynq: DT: Fix coding style issues in dtsi
  ARM: zynq: DT: Describe interrupt-names for pl330
  ARM: zynq: DT: Extend compatible string for zedboard
  ARM: zynq: DT: Use 0x prefix for memory nodes
  ARM: zynq: DT: Update years in header
  ARM: zynq: DT: Move size/address properties to dtsi
  ARM: zynq: DT: Fix Ethernet phy modes
  ARM: zynq: DT: Add LEDs to zc702 DT
This commit is contained in:
Arnd Bergmann 2014-09-25 17:47:26 +02:00
parent 2d3a2cdbbd 6f752f70a3
commit 41c9002ad1
5 changed files with 67 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/boot/dts/zynq-7000.dtsi
View File

@ -195,6 +195,8 @@
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gem1: ethernet@e000c000 {
@ -204,6 +206,8 @@
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
sdhci0: sdhci@e0100000 {
@ -214,7 +218,7 @@
interrupt-parent = <&intc>;
interrupts = <0 24 4>;
reg = <0xe0100000 0x1000>;
} ;
};
sdhci1: sdhci@e0101000 {
compatible = "arasan,sdhci-8.9a";
@ -224,7 +228,7 @@
interrupt-parent = <&intc>;
interrupts = <0 47 4>;
reg = <0xe0101000 0x1000>;
} ;
};
slcr: slcr@f8000000 {
#address-cells = <1>;
@ -256,6 +260,8 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
"dma4", "dma5", "dma6", "dma7";
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
@ -271,7 +277,7 @@
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
} ;
};
global_timer: timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
@ -303,6 +309,6 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
} ;
};
};
};

27
arch/arm/boot/dts/zynq-parallella.dts
View File

@ -25,7 +25,7 @@
memory {
device_type = "memory";
reg = <0 0x40000000>;
reg = <0x0 0x40000000>;
};
chosen {
@ -38,8 +38,6 @@
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy: ethernet-phy@0 {
/* Marvell 88E1318 */
@ -53,6 +51,29 @@
&i2c0 {
status = "okay";
isl9305: isl9305@68 {
compatible = "isl,isl9305";
reg = <0x68>;
regulators {
dcd1 {
regulator-name = "VDD_DSP";
regulator-always-on;
};
dcd2 {
regulator-name = "1P35V";
regulator-always-on;
};
ldo1 {
regulator-name = "VDD_ADJ";
};
ldo2 {
regulator-name = "VDD_GPIO";
regulator-always-on;
};
};
};
};
&sdhci1 {

18
arch/arm/boot/dts/zynq-zc702.dts
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2011 Xilinx
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
* This software is licensed under the terms of the GNU General Public
@ -27,6 +27,15 @@
bootargs = "console=ttyPS0,115200 earlyprintk";
};
leds {
compatible = "gpio-leds";
ds23 {
label = "ds23";
gpios = <&gpio0 10 0>;
linux,default-trigger = "heartbeat";
};
};
};
&can0 {
@ -35,7 +44,12 @@
&gem0 {
status = "okay";
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
};
};
&i2c0 {

12
arch/arm/boot/dts/zynq-zc706.dts
View File

@ -1,7 +1,6 @@
/*
* Copyright (C) 2011 Xilinx
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
* Copyright (C) 2013 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@ -21,7 +20,7 @@
memory {
device_type = "memory";
reg = <0 0x40000000>;
reg = <0x0 0x40000000>;
};
chosen {
@ -32,7 +31,12 @@
&gem0 {
status = "okay";
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
};
};
&i2c0 {

14
arch/arm/boot/dts/zynq-zed.dts
View File

@ -1,7 +1,6 @@
/*
* Copyright (C) 2011 Xilinx
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
* Copyright (C) 2013 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@ -17,11 +16,11 @@
/ {
model = "Zynq Zed Development Board";
compatible = "xlnx,zynq-7000";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
memory {
device_type = "memory";
reg = <0 0x20000000>;
reg = <0x0 0x20000000>;
};
chosen {
@ -32,7 +31,12 @@
&gem0 {
status = "okay";
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0>;
};
};
&sdhci0 {