platform/chrome: cros_ec_lpc: Merge cros_ec_lpc and cros_ec_lpc_reg
The cros_ec_lpc_reg files are only used by the cros_ec_lpc core and there isn't logical separation between them. So, merge those files into the cros_ec_lpc also allowing us to drop the header file used for the interface between the two. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Nick Crews <ncrews@chromium.org>
This commit is contained in:
Enric Balletbo i Serra
parent
d096aa3eb6
commit
4116fd25c5
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@ -10,7 +10,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
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obj-$(CONFIG_CROS_EC_ISHTP) += cros_ec_ishtp.o
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obj-$(CONFIG_CROS_EC_RPMSG) += cros_ec_rpmsg.o
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obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
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cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_reg.o
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cros_ec_lpcs-objs := cros_ec_lpc.o
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cros_ec_lpcs-$(CONFIG_CROS_EC_LPC_MEC) += cros_ec_lpc_mec.o
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obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o
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obj-$(CONFIG_CROS_EC_PROTO) += cros_ec_proto.o cros_ec_trace.o
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@ -23,7 +23,7 @@
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#include <linux/printk.h>
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#include <linux/suspend.h>
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#include "cros_ec_lpc_reg.h"
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#include "cros_ec_lpc_mec.h"
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#define DRV_NAME "cros_ec_lpcs"
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#define ACPI_DRV_NAME "GOOG0004"
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@ -31,6 +31,101 @@
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/* True if ACPI device is present */
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static bool cros_ec_lpc_acpi_device_found;
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static u8 lpc_read_bytes(unsigned int offset, unsigned int length, u8 *dest)
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{
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int sum = 0;
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int i;
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for (i = 0; i < length; ++i) {
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dest[i] = inb(offset + i);
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sum += dest[i];
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}
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/* Return checksum of all bytes read */
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return sum;
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}
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static u8 lpc_write_bytes(unsigned int offset, unsigned int length, u8 *msg)
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{
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int sum = 0;
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int i;
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for (i = 0; i < length; ++i) {
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outb(msg[i], offset + i);
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sum += msg[i];
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}
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/* Return checksum of all bytes written */
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return sum;
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}
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#ifdef CONFIG_CROS_EC_LPC_MEC
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static u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length,
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u8 *dest)
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{
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int in_range = cros_ec_lpc_mec_in_range(offset, length);
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if (in_range < 0)
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return 0;
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return in_range ?
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cros_ec_lpc_io_bytes_mec(MEC_IO_READ,
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offset - EC_HOST_CMD_REGION0,
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length, dest) :
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lpc_read_bytes(offset, length, dest);
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}
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static u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length,
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u8 *msg)
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{
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int in_range = cros_ec_lpc_mec_in_range(offset, length);
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if (in_range < 0)
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return 0;
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return in_range ?
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cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE,
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offset - EC_HOST_CMD_REGION0,
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length, msg) :
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lpc_write_bytes(offset, length, msg);
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}
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static void cros_ec_lpc_reg_init(void)
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{
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cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0,
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EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE);
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}
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static void cros_ec_lpc_reg_destroy(void)
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{
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cros_ec_lpc_mec_destroy();
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}
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#else /* CONFIG_CROS_EC_LPC_MEC */
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static u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length,
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u8 *dest)
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{
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return lpc_read_bytes(offset, length, dest);
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}
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static u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length,
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u8 *msg)
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{
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return lpc_write_bytes(offset, length, msg);
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}
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static void cros_ec_lpc_reg_init(void)
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{
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}
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static void cros_ec_lpc_reg_destroy(void)
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{
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}
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#endif /* CONFIG_CROS_EC_LPC_MEC */
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static int ec_response_timed_out(void)
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{
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unsigned long one_second = jiffies + HZ;
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@ -1,101 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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// LPC interface for ChromeOS Embedded Controller
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//
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// Copyright (C) 2016 Google, Inc
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#include <linux/io.h>
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#include <linux/mfd/cros_ec.h>
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#include <linux/mfd/cros_ec_commands.h>
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#include "cros_ec_lpc_mec.h"
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static u8 lpc_read_bytes(unsigned int offset, unsigned int length, u8 *dest)
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{
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int i;
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int sum = 0;
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for (i = 0; i < length; ++i) {
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dest[i] = inb(offset + i);
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sum += dest[i];
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}
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/* Return checksum of all bytes read */
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return sum;
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}
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static u8 lpc_write_bytes(unsigned int offset, unsigned int length, u8 *msg)
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{
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int i;
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int sum = 0;
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for (i = 0; i < length; ++i) {
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outb(msg[i], offset + i);
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sum += msg[i];
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}
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/* Return checksum of all bytes written */
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return sum;
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}
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#ifdef CONFIG_CROS_EC_LPC_MEC
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u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, u8 *dest)
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{
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int in_range = cros_ec_lpc_mec_in_range(offset, length);
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if (in_range < 0)
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return 0;
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return in_range ?
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cros_ec_lpc_io_bytes_mec(MEC_IO_READ,
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offset - EC_HOST_CMD_REGION0,
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length, dest) :
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lpc_read_bytes(offset, length, dest);
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}
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u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, u8 *msg)
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{
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int in_range = cros_ec_lpc_mec_in_range(offset, length);
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if (in_range < 0)
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return 0;
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return in_range ?
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cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE,
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offset - EC_HOST_CMD_REGION0,
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length, msg) :
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lpc_write_bytes(offset, length, msg);
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}
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void cros_ec_lpc_reg_init(void)
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{
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cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0,
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EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE);
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}
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void cros_ec_lpc_reg_destroy(void)
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{
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cros_ec_lpc_mec_destroy();
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}
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#else /* CONFIG_CROS_EC_LPC_MEC */
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u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, u8 *dest)
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{
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return lpc_read_bytes(offset, length, dest);
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}
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u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, u8 *msg)
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{
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return lpc_write_bytes(offset, length, msg);
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}
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void cros_ec_lpc_reg_init(void)
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{
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}
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void cros_ec_lpc_reg_destroy(void)
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{
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}
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#endif /* CONFIG_CROS_EC_LPC_MEC */
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@ -1,45 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* LPC interface for ChromeOS Embedded Controller
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*
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* Copyright (C) 2016 Google, Inc
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*/
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#ifndef __CROS_EC_LPC_REG_H
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#define __CROS_EC_LPC_REG_H
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/**
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* cros_ec_lpc_read_bytes - Read bytes from a given LPC-mapped address.
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* Returns 8-bit checksum of all bytes read.
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*
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* @offset: Base read address
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* @length: Number of bytes to read
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* @dest: Destination buffer
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*/
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u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, u8 *dest);
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/**
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* cros_ec_lpc_write_bytes - Write bytes to a given LPC-mapped address.
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* Returns 8-bit checksum of all bytes written.
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*
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* @offset: Base write address
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* @length: Number of bytes to write
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* @msg: Write data buffer
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*/
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u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, u8 *msg);
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/**
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* cros_ec_lpc_reg_init
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*
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* Initialize register I/O.
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*/
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void cros_ec_lpc_reg_init(void);
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/**
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* cros_ec_lpc_reg_destroy
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*
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* Cleanup reg I/O.
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*/
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void cros_ec_lpc_reg_destroy(void);
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#endif /* __CROS_EC_LPC_REG_H */
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