mlxsw: pci: Check number of CQEs for CQE version 2
Check number of CQEs for CQE version 2 reported by QUERY_AQ_CAP command. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -424,10 +424,15 @@ MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8);
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MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8);
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/* cmd_mbox_query_aq_cap_log_max_cq_sz
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* Log (base 2) of max CQEs allowed on CQ.
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* Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1.
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*/
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MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8);
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/* cmd_mbox_query_aq_cap_log_max_cqv2_sz
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* Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2.
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*/
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MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8);
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/* cmd_mbox_query_aq_cap_max_num_cqs
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* Maximum number of CQs.
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*/
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@ -959,6 +959,7 @@ static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
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u8 rdq_log2sz;
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u8 num_cqs;
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u8 cq_log2sz;
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u8 cqv2_log2sz;
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u8 num_eqs;
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u8 eq_log2sz;
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int err;
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@ -974,6 +975,7 @@ static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
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rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
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num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
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cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
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cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
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num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
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eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
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@ -986,6 +988,8 @@ static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
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if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
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(1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
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(1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) ||
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(mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 &&
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(1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) ||
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(1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
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dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
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return -EINVAL;
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