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drm/amd/display: updated wm table for Renoir 

[Why]
For certain timings, Renoir may underflow due to sr exit
latency being too slow.

[How]
Updated wm table for renoir.

Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jake Wang 2020-12-03 14:05:56 -05:00 committed by Alex Deucher
parent 5200c4017e
commit 410066d24c
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
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@ -746,24 +746,24 @@ static struct wm_table ddr4_wm_table_rn = {
.wm_inst = WM_B, .wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72, .pstate_latency_us = 11.72,
.sr_exit_time_us = 10.12, .sr_exit_time_us = 11.12,
.sr_enter_plus_exit_time_us = 11.48, .sr_enter_plus_exit_time_us = 12.48,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_C, .wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72, .pstate_latency_us = 11.72,
.sr_exit_time_us = 10.12, .sr_exit_time_us = 11.12,
.sr_enter_plus_exit_time_us = 11.48, .sr_enter_plus_exit_time_us = 12.48,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_D, .wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72, .pstate_latency_us = 11.72,
.sr_exit_time_us = 10.12, .sr_exit_time_us = 11.12,
.sr_enter_plus_exit_time_us = 11.48, .sr_enter_plus_exit_time_us = 12.48,
.valid = true, .valid = true,
}, },
} }