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drm/amdgpu: update psp fw loading sequence 

Added dedicated function to check if particular fw should be skipped from loading.

Added dedicated function for SMU FW loading via PSP

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
John Clements 2020-04-14 15:21:35 +08:00 committed by Alex Deucher
parent 47c11cff7e
commit 40e611bdd1
1 changed files with 77 additions and 49 deletions
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126
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
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@ -42,6 +42,8 @@ static void psp_set_funcs(struct amdgpu_device *adev);
static int psp_sysfs_init(struct amdgpu_device *adev); static int psp_sysfs_init(struct amdgpu_device *adev);
static void psp_sysfs_fini(struct amdgpu_device *adev); static void psp_sysfs_fini(struct amdgpu_device *adev);
static int psp_load_smu_fw(struct psp_context *psp);
/* /*
* Due to DF Cstate management centralized to PMFW, the firmware * Due to DF Cstate management centralized to PMFW, the firmware
* loading sequence will be updated as below: * loading sequence will be updated as below:
@ -1175,16 +1177,20 @@ static int psp_hw_start(struct psp_context *psp)
} }
/* /*
* For those ASICs with DF Cstate management centralized * For ASICs with DF Cstate management centralized
* to PMFW, TMR setup should be performed after PMFW * to PMFW, TMR setup should be performed after PMFW
* loaded and before other non-psp firmware loaded. * loaded and before other non-psp firmware loaded.
*/ */
if (!psp->pmfw_centralized_cstate_management) { if (psp->pmfw_centralized_cstate_management) {
ret = psp_tmr_load(psp); ret = psp_load_smu_fw(psp);
if (ret) { if (ret)
DRM_ERROR("PSP load tmr failed!\n");
return ret; return ret;
} }
ret = psp_tmr_load(psp);
if (ret) {
DRM_ERROR("PSP load tmr failed!\n");
return ret;
} }
return 0; return 0;
@ -1361,7 +1367,7 @@ static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
} }
static int psp_execute_np_fw_load(struct psp_context *psp, static int psp_execute_np_fw_load(struct psp_context *psp,
struct amdgpu_firmware_info *ucode) struct amdgpu_firmware_info *ucode)
{ {
int ret = 0; int ret = 0;
@ -1375,64 +1381,86 @@ static int psp_execute_np_fw_load(struct psp_context *psp,
return ret; return ret;
} }
static int psp_load_smu_fw(struct psp_context *psp)
{
int ret;
struct amdgpu_firmware_info *ucode =
&psp->adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
return 0;
ret = psp_execute_np_fw_load(psp, ucode);
if (ret)
DRM_ERROR("PSP load smu failed!\n");
return ret;
}
static bool fw_load_skip_check(struct psp_context *psp,
struct amdgpu_firmware_info *ucode)
{
if (!ucode->fw)
return true;
if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
(psp_smu_reload_quirk(psp) ||
psp->autoload_supported ||
psp->pmfw_centralized_cstate_management))
return true;
if (amdgpu_sriov_vf(psp->adev) &&
(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
|| ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
/*skip ucode loading in SRIOV VF */
return true;
if (psp->autoload_supported &&
(ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
/* skip mec JT when autoload is enabled */
return true;
return false;
}
static int psp_np_fw_load(struct psp_context *psp) static int psp_np_fw_load(struct psp_context *psp)
{ {
int i, ret; int i, ret;
struct amdgpu_firmware_info *ucode; struct amdgpu_firmware_info *ucode;
struct amdgpu_device* adev = psp->adev; struct amdgpu_device* adev = psp->adev;
if (psp->autoload_supported || if (psp->autoload_supported &&
psp->pmfw_centralized_cstate_management) { !psp->pmfw_centralized_cstate_management) {
ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; ret = psp_load_smu_fw(psp);
if (!ucode->fw || amdgpu_sriov_vf(adev))
goto out;
ret = psp_execute_np_fw_load(psp, ucode);
if (ret) if (ret)
return ret; return ret;
} }
if (psp->pmfw_centralized_cstate_management) {
ret = psp_tmr_load(psp);
if (ret) {
DRM_ERROR("PSP load tmr failed!\n");
return ret;
}
}
out:
for (i = 0; i < adev->firmware.max_ucodes; i++) { for (i = 0; i < adev->firmware.max_ucodes; i++) {
ucode = &adev->firmware.ucode[i]; ucode = &adev->firmware.ucode[i];
if (!ucode->fw)
continue;
if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
(psp_smu_reload_quirk(psp) || !fw_load_skip_check(psp, ucode)) {
psp->autoload_supported || ret = psp_load_smu_fw(psp);
psp->pmfw_centralized_cstate_management)) if (ret)
return ret;
continue; continue;
}
if (amdgpu_sriov_vf(adev) && if (fw_load_skip_check(psp, ucode))
(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
|| ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
/*skip ucode loading in SRIOV VF */
continue;
if (psp->autoload_supported &&
(ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
/* skip mec JT when autoload is enabled */
continue; continue;
psp_print_fw_hdr(psp, ucode); psp_print_fw_hdr(psp, ucode);