From 67d62e5a3b55d470101eff378f5cb7437de0f26a Mon Sep 17 00:00:00 2001 From: Evan Green Date: Thu, 6 Dec 2018 10:45:21 -0800 Subject: [PATCH 01/14] arm64: dts: qcom: sdm845: Add SD node Add one of the two SD controllers to SDM845. Reviewed-by: Douglas Anderson Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c27cbd3bcb0a..5e5544cb80ab 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1348,6 +1348,21 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + status = "disabled"; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy"; reg = <0x88e2000 0x400>; From b454dbdb8f067288bee409c5e9f3101004b83125 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Thu, 6 Dec 2018 10:45:22 -0800 Subject: [PATCH 02/14] arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtp Enable support for one of the micro SD slots on the MTP. Reviewed-by: Douglas Anderson Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 58 ++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index b3def0358177..cde76da42cbb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include "sdm845.dtsi" @@ -358,8 +359,16 @@ status = "okay"; }; -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; + + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; }; &uart9 { @@ -450,3 +459,48 @@ bias-pull-up; }; }; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + sdc2_clk: sdc2-clk { + pinconf { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; + }; + }; + + sdc2_cmd: sdc2-cmd { + pinconf { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sdc2_data: sdc2-data { + pinconf { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sd_card_det_n: sd-card-det-n { + pinmux { + pins = "gpio126"; + function = "gpio"; + }; + + pinconf { + pins = "gpio126"; + bias-pull-up; + }; + }; +}; From 4429e57567bb728ba1c81332e7e68d898e510d1c Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Thu, 11 Oct 2018 15:19:30 +0530 Subject: [PATCH 03/14] arm64: dts: sdm845: Add node for arm,mmu-500 Add device node for arm,mmu-500 available on sdm845. This MMU-500 with single TCU and multiple TBU architecture is shared among all the peripherals except gpu. Signed-off-by: Vivek Gautam Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 72 ++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5e5544cb80ab..0f3d84af949d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1590,6 +1590,78 @@ cell-index = <0>; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + apss_shared: mailbox@17990000 { compatible = "qcom,sdm845-apss-shared"; reg = <0x17990000 0x1000>; From cc16687fbd740431d9f9ebbfb64ace51676b9d3b Mon Sep 17 00:00:00 2001 From: Evan Green Date: Mon, 10 Dec 2018 11:28:24 -0800 Subject: [PATCH 04/14] arm64: dts: qcom: sdm845: add UFS controller Add the UFS controller and PHY to SDM845. Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Douglas Anderson [bjorn: Add iommu context for the host controller] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0f3d84af949d..d92dd49ed2c3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -981,6 +981,72 @@ }; }; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sdm845-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x1d84000 0x2500>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0x100 0xf>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1d87000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0x1d87400 0x108>, + <0x1d87600 0x1e0>, + <0x1d87c00 0x1dc>, + <0x1d87800 0x108>, + <0x1d87a00 0x1e0>; + #phy-cells = <0>; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x40000>; From b010fdb4ea58fb1a0c59c550ef5692745b1e4dc2 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Mon, 10 Dec 2018 11:28:25 -0800 Subject: [PATCH 05/14] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Enable the UFS host controller and PHY on sdm845-mtp. Reviewed-by: Vivek Gautam Reviewed-by: Douglas Anderson Signed-off-by: Can Guo Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index cde76da42cbb..55292f2f1552 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -375,6 +375,20 @@ status = "okay"; }; +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + &usb_1 { status = "okay"; }; From 9ebfcba1ac46841a60813b4e172108215b4f1525 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Mon, 10 Dec 2018 11:28:26 -0800 Subject: [PATCH 06/14] arm64: dts: qcom: sdm845: Add USB PHY lane two Add the second lane registers for the USB PHY, now that the QMP phy bindings have been updated. This way the driver can stop reaching beyond its register region to get at the second lane. Reviewed-by: Douglas Anderson Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d92dd49ed2c3..738345e27d36 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1480,10 +1480,12 @@ <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: lane@88e9200 { + usb_1_ssphy: lanes@88e9200 { reg = <0x88e9200 0x128>, <0x88e9400 0x200>, <0x88e9c00 0x218>, + <0x88e9600 0x128>, + <0x88e9800 0x200>, <0x88e9a00 0x100>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; From c604b82a09ce3244add85064f8538d45f879a980 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 21 Dec 2018 23:44:23 +0530 Subject: [PATCH 07/14] arm64: dts: sdm845: Add cpufreq device node This change adds the cpufreq node as per the bindings example for SDM845. Reviewed-by: Matthias Kaehlcke Signed-off-by: Taniya Das Tested-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 738345e27d36..d9be5bba62c4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -99,6 +99,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x0>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -114,6 +115,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_100>; L2_100: l2-cache { compatible = "cache"; @@ -126,6 +128,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_200>; L2_200: l2-cache { compatible = "cache"; @@ -138,6 +141,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; @@ -150,6 +154,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x400>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_400>; L2_400: l2-cache { compatible = "cache"; @@ -162,6 +167,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x500>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_500>; L2_500: l2-cache { compatible = "cache"; @@ -174,6 +180,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x600>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_600>; L2_600: l2-cache { compatible = "cache"; @@ -186,6 +193,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x700>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_700>; L2_700: l2-cache { compatible = "cache"; @@ -1836,6 +1844,17 @@ status = "disabled"; }; }; + + cpufreq_hw: cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; thermal-zones { From f72281126815389f63e88fb8916fdf64631d1caf Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 3 Jan 2019 21:34:55 +0100 Subject: [PATCH 08/14] arm64: dts: qcom: qcs404: sdcc1: enable HS400 The controller can support EXT_CSD_CARD_TYPE_HS400_1_8V cards. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a39924efebe4..2c2c9b00c022 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -127,6 +127,7 @@ status = "ok"; mmc-ddr-1_8v; + mmc-hs400-1_8v; bus-width = <8>; non-removable; From 4bbbca1e7fea961084eaa0a58cd126f969dd3901 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Tue, 27 Nov 2018 20:47:16 +0530 Subject: [PATCH 09/14] arm64: dts: qcom: qcs404: Add WCN3990 WLAN module device node Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on qcs404 soc. Optional clock and regulator controls are not yet available in upstream, hence add them once available. Reviewed-by: Vinod Koul Signed-off-by: Govind Singh Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2c2c9b00c022..ba4152318854 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -187,3 +187,7 @@ }; }; }; + +&wifi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9b5c16562bbe..f3d77e7ee0d2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -346,6 +346,26 @@ status = "okay"; }; + wifi: wifi@a000000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0xa000000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; From 041b9a7b9fdbe4f12c2e48ead3d45ef67d830cd6 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 12 Dec 2018 15:47:55 +0530 Subject: [PATCH 10/14] arm64: dts: pms405: Export PMIC temperature to thermal framework The PMS405 PMIC has an ADC that exposes the on-die temperature that we wire up to spmi-temp-alarm thermal driver. This allows the PMIC temperature to be exposed to Linux through the thermal framework. Signed-off-by: Amit Kucheria Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pms405.dtsi | 79 ++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index ad2b62dfc9f6..1bb836d1e8aa 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -3,6 +3,32 @@ #include #include +#include +#include + +/ { + thermal-zones { + pms405 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pms405_temp>; + + trips { + pms405_alert0: pms405-alert0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + pms405_crit: pms405-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; &spmi_bus { pms405_0: pms405@0 { @@ -45,6 +71,59 @@ }; }; + pms405_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pms405_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pms405_adc: adc@3100 { + compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + ref_gnd { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + qcom,pre-scaling = <1 3>; + }; + + die_temp { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + xo_therm_100k_pu { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + amux_thm1_100k_pu { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + amux_thm3_100k_pu { + reg = ; + qcom,pre-scaling = <1 1>; + }; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; From af61bef513ba179559e56908b8c465e587bc3890 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 14 Dec 2018 12:01:02 +0100 Subject: [PATCH 11/14] arm64: dts: apq8016-sbc: Increase load on l11 for SDCARD In the same way as for msm8974-hammerhead, l11 load, used for SDCARD VMMC, needs to be increased in order to prevent any voltage drop issues (due to limited current) happening with some SDCARDS or during specific operations (e.g. write). Tested on Dragonboard-410c and DART-SD410 boards. Fixes: 4c7d53d16d77 (arm64: dts: apq8016-sbc: add regulators support) Reported-by: Manabu Igusa Signed-off-by: Loic Poulain Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 46feedf7c989..134617d87a1a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -644,6 +644,8 @@ l11 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <3337000>; + regulator-allow-set-load; + regulator-system-load = <200000>; }; l12 { From ff10032fb309d0baa0b79e28009bf154de08d341 Mon Sep 17 00:00:00 2001 From: Jakob Wuhrer Date: Fri, 14 Dec 2018 18:01:30 +0100 Subject: [PATCH 12/14] arm64: dts: qcom: Correct "gpiio" typo in msm8996-pins gpiio5 is missspelt in msm8996-pins.dtsi, fix that. Signed-off-by: Jakob Wuhrer Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 8d5114d16d09..131878db9852 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -139,7 +139,7 @@ }; pinconf { - pins = "gpio4", "gpiio5", "gpio6", "gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; drive-strength = <2>; bias-disable; }; From 0f60e6fb54fb2d749e701d910de7f39f67c0020c Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 23 Nov 2018 09:44:38 +0100 Subject: [PATCH 13/14] arm64: dts: qcom: pm8916: Add PON watchdog node Add watchdog child node to the PM8916 PON device. Signed-off-by: Loic Poulain Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 15a37cbcd216..9dd2df1cbf47 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -32,6 +32,12 @@ bias-pull-up; linux,code = ; }; + + watchdog { + compatible = "qcom,pm8916-wdt"; + interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; + timeout-sec = <60>; + }; }; pm8916_gpios: gpios@c000 { From 08c2a076d18f3e481c004f59a9c4c9f07eec01db Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 4 Dec 2018 15:54:12 -0800 Subject: [PATCH 14/14] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file DPU is short for the Display Processing Unit. It is the display controller on Qualcomm SDM845 chips. This change adds MDSS and DSI nodes to enable display on the target device. Changes in v2: - Beefed up commit message - Use SoC specific compatibles for mdss and dpu (Rob H) - Use assigned-clocks to set initial clock frequency(Rob H) Changes in v3: - added IOMMU node - Fix device naming (remove _phys) - Use correct IRQ_TYPE in interrupt specifiers Changes in v4: - move mdss node to preserve the unit address sort order - remove _clk suffix from dsi clocks (both the comments are from Doug Anderson) Changes in v5: - Keep the device status "disabled" by default (Bjorn Andersson) - Use MDSS_GDSC macro (Jordan) - Fix phy-names (Jordan) - List reg ranges in numerical order (Jordan) Changes in v6: - Separating this patch out of the series - fix phy-names Signed-off-by: Jeykumar Sankaran Signed-off-by: Sean Paul Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 203 +++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d9be5bba62c4..f19353414eda 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1617,6 +1617,209 @@ }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae94400 0x200>, + <0xae94600 0x280>, + <0xae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae96400 0x200>, + <0xae96600 0x280>, + <0xae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0xaf00000 0x10000>;