From 16532759d48a9fcf96cccb013b7f4dc338c2f2d6 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Mon, 19 Aug 2013 05:16:59 +0900 Subject: [PATCH 1/6] ARM: SAMSUNG: Fix switching FIFO in arch_enable_uart_fifo function When CONFIG_S3C_BOOT_UART_FORCE_FIFO symbol is set, we should enable FIFO but actually switch command is missing in the code. This patch adds this switching. Signed-off-by: Alexander Shiyan Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/include/plat/uncompress.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 4afc32f90b6d..f48dc0a4736c 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -145,6 +145,8 @@ static inline void arch_enable_uart_fifo(void) if (!(fifocon & S3C2410_UFCON_RESETBOTH)) break; } + + uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE); } } #else From 05118a8e1435c2706d63e8411390d6e16e13e17c Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 06:49:53 +0900 Subject: [PATCH 2/6] ARM: dts: Add missing op_mode property to PMIC on Arndale Though the default value is 1, add it explicitly to avoid unnecessary boot warnings and for consistency. Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 684527087aa4..bbfb23f942e1 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -302,11 +302,13 @@ buck7_reg: BUCK7 { regulator-name = "PVDD_BUCK7"; regulator-always-on; + op_mode = <1>; }; buck8_reg: BUCK8 { regulator-name = "PVDD_BUCK8"; regulator-always-on; + op_mode = <1>; }; buck9_reg: BUCK9 { From 0da805639fac5bf729b4880ee14c4abff2c202d0 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 06:54:34 +0900 Subject: [PATCH 3/6] ARM: dts: Add missing frequency property to exynos5250 Added missing clock frequency property to CPU node to avoid boot time warnings. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9db5047812f3..d871e6241d8a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -60,11 +60,13 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + clock-frequency = <1700000000>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + clock-frequency = <1700000000>; }; }; From 505d41ecbc650afd1724403754694e662e1ba0da Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 06:58:37 +0900 Subject: [PATCH 4/6] ARM: dts: Fix a typo in exynos5420-pinctrl.dtsi Fixed samaung -> samsung in property name. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index e695aba5f73c..e62c8eb57438 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -64,7 +64,7 @@ samsung,pins = "gpx0-7"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samaung,pin-drv = <0>; + samsung,pin-drv = <0>; }; }; From 67ddd05382d98a106b75dba47f7550456ab5f832 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Thu, 12 Dec 2013 07:45:07 +0900 Subject: [PATCH 5/6] ARM: dts: Update display clock frequency for Origen-4210 As per the timing information for supported panel, the value should be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate. Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152 Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683 Target pixel clock rate for refresh rate @60 Hz = 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz Signed-off-by: Tushar Behera Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-origen.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 1a12fb23767c..2aa13cb3bbed 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -313,7 +313,7 @@ display-timings { native-mode = <&timing0>; timing0: timing { - clock-frequency = <50000>; + clock-frequency = <47500000>; hactive = <1024>; vactive = <600>; hfront-porch = <64>; From 236940d2c951a84735fdd7b958b5159eaf501784 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 07:45:12 +0900 Subject: [PATCH 6/6] ARM: dts: Update display clock frequency for Origen-4412 As per the timing information for supported panel, the value should be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate. Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152 Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683 Target pixel clock rate for refresh rate @60 Hz = 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-origen.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index d65984c440f6..95201559c3ad 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -159,7 +159,7 @@ display-timings { native-mode = <&timing0>; timing0: timing { - clock-frequency = <50000>; + clock-frequency = <47500000>; hactive = <1024>; vactive = <600>; hfront-porch = <64>;