drm/amdgpu: Add field in amdgpu_dev to hold reserved doorbell index
This is a preparation work to make reserved doorbell index per device, instead of using a global macro definition. By doing this, we can easily change doorbell layout for future ASICs while not affecting ASICs in production. Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -810,6 +810,55 @@ struct amd_powerplay {
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uint32_t pp_feature;
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};
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/* Reserved doorbells for amdgpu (including multimedia).
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* KFD can use all the rest in the 2M doorbell bar.
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* For asic before vega10, doorbell is 32-bit, so the
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* index/offset is in dword. For vega10 and after, doorbell
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* can be 64-bit, so the index defined is in qword.
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*/
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struct amdgpu_doorbell_index {
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uint32_t kiq;
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uint32_t mec_ring0;
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uint32_t mec_ring1;
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uint32_t mec_ring2;
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uint32_t mec_ring3;
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uint32_t mec_ring4;
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uint32_t mec_ring5;
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uint32_t mec_ring6;
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uint32_t mec_ring7;
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uint32_t userqueue_start;
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uint32_t userqueue_end;
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uint32_t gfx_ring0;
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uint32_t sdma_engine0;
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uint32_t sdma_engine1;
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uint32_t sdma_engine2;
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uint32_t sdma_engine3;
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uint32_t sdma_engine4;
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uint32_t sdma_engine5;
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uint32_t sdma_engine6;
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uint32_t sdma_engine7;
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uint32_t ih;
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union {
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struct {
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uint32_t vcn_ring0_1;
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uint32_t vcn_ring2_3;
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uint32_t vcn_ring4_5;
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uint32_t vcn_ring6_7;
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} vcn;
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struct {
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uint32_t uvd_ring0_1;
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uint32_t uvd_ring2_3;
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uint32_t uvd_ring4_5;
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uint32_t uvd_ring6_7;
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uint32_t vce_ring0_1;
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uint32_t vce_ring2_3;
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uint32_t vce_ring4_5;
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uint32_t vce_ring6_7;
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} uvd_vce;
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};
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uint32_t max_assignment;
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};
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#define AMDGPU_RESET_MAGIC_NUM 64
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struct amdgpu_device {
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struct device *dev;
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@ -1023,6 +1072,7 @@ struct amdgpu_device {
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unsigned long last_mm_index;
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bool in_gpu_reset;
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struct mutex lock_reset;
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struct amdgpu_doorbell_index doorbell_index;
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};
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static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
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