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ethtool: Add support for 800Gbps link modes 

Add support for 800Gbps speed, link modes of 100Gbps per lane.
As mentioned in slide 21 in IEEE documentation [1], all adopted 802.3df
copper and optical PMDs baselines using 100G/lane will be supported.

Add the relevant PMDs which are mentioned in slide 5 in IEEE
documentation [1] and were approved on 10-2022 [2]:
BP - KR8
Cu Cable - CR8
MMF 50m - VR8
MMF 100m - SR8
SMF 500m - DR8
SMF 2km - DR8-2

[1]: https://www.ieee802.org/3/df/public/22_10/22_1004/shrikhande_3df_01a_221004.pdf
[2]: https://ieee802.org/3/df/KeyMotions_3df_221005.pdf

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Cohen 2022-10-20 17:20:03 +02:00 committed by David S. Miller
parent c1aa0a9078
commit 404c76783f
3 changed files with 32 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/net/phy/phy-core.c
View File

@ -13,7 +13,7 @@
*/ */
const char *phy_speed_to_str(int speed) const char *phy_speed_to_str(int speed)
{ {
BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93, BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str " "If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n"); "and the PHY settings array.\n");
@ -49,6 +49,8 @@ const char *phy_speed_to_str(int speed)
return "200Gbps"; return "200Gbps";
case SPEED_400000: case SPEED_400000:
return "400Gbps"; return "400Gbps";
case SPEED_800000:
return "800Gbps";
case SPEED_UNKNOWN: case SPEED_UNKNOWN:
return "Unknown"; return "Unknown";
default: default:
@ -157,6 +159,13 @@ EXPORT_SYMBOL_GPL(phy_interface_num_ports);
.bit = ETHTOOL_LINK_MODE_ ## b ## _BIT} .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
static const struct phy_setting settings[] = { static const struct phy_setting settings[] = {
/* 800G */
PHY_SETTING( 800000, FULL, 800000baseCR8_Full ),
PHY_SETTING( 800000, FULL, 800000baseKR8_Full ),
PHY_SETTING( 800000, FULL, 800000baseDR8_Full ),
PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ),
PHY_SETTING( 800000, FULL, 800000baseSR8_Full ),
PHY_SETTING( 800000, FULL, 800000baseVR8_Full ),
/* 400G */ /* 400G */
PHY_SETTING( 400000, FULL, 400000baseCR8_Full ), PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseKR8_Full ), PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),

8
include/uapi/linux/ethtool.h
View File

@ -1737,6 +1737,13 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90, ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91, ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92, ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,
ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,
ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,
ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,
ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,
ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,
ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,
/* must be last entry */ /* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS __ETHTOOL_LINK_MODE_MASK_NBITS
}; };
@ -1848,6 +1855,7 @@ enum ethtool_link_mode_bit_indices {
#define SPEED_100000 100000 #define SPEED_100000 100000
#define SPEED_200000 200000 #define SPEED_200000 200000
#define SPEED_400000 400000 #define SPEED_400000 400000
#define SPEED_800000 800000
#define SPEED_UNKNOWN -1 #define SPEED_UNKNOWN -1

14
net/ethtool/common.c
View File

@ -202,6 +202,12 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(100, FX, Half), __DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full), __DEFINE_LINK_MODE_NAME(100, FX, Full),
__DEFINE_LINK_MODE_NAME(10, T1L, Full), __DEFINE_LINK_MODE_NAME(10, T1L, Full),
__DEFINE_LINK_MODE_NAME(800000, CR8, Full),
__DEFINE_LINK_MODE_NAME(800000, KR8, Full),
__DEFINE_LINK_MODE_NAME(800000, DR8, Full),
__DEFINE_LINK_MODE_NAME(800000, DR8_2, Full),
__DEFINE_LINK_MODE_NAME(800000, SR8, Full),
__DEFINE_LINK_MODE_NAME(800000, VR8, Full),
}; };
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
@ -238,6 +244,8 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
#define __LINK_MODE_LANES_X 1 #define __LINK_MODE_LANES_X 1
#define __LINK_MODE_LANES_FX 1 #define __LINK_MODE_LANES_FX 1
#define __LINK_MODE_LANES_T1L 1 #define __LINK_MODE_LANES_T1L 1
#define __LINK_MODE_LANES_VR8 8
#define __LINK_MODE_LANES_DR8_2 8
#define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \ #define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \
[ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \ [ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \
@ -352,6 +360,12 @@ const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(100, FX, Half), __DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full), __DEFINE_LINK_MODE_PARAMS(100, FX, Full),
__DEFINE_LINK_MODE_PARAMS(10, T1L, Full), __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
__DEFINE_LINK_MODE_PARAMS(800000, CR8, Full),
__DEFINE_LINK_MODE_PARAMS(800000, KR8, Full),
__DEFINE_LINK_MODE_PARAMS(800000, DR8, Full),
__DEFINE_LINK_MODE_PARAMS(800000, DR8_2, Full),
__DEFINE_LINK_MODE_PARAMS(800000, SR8, Full),
__DEFINE_LINK_MODE_PARAMS(800000, VR8, Full),
}; };
static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS); static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);