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media: camss: vfe: Add support for VFE 4.8 

Add the support for VFE 4.8 in the camss-vfe-4-7 driver, as this one
really is a minor revision, requiring the very same management and
basically having the same register layout as VFE 4.7, but needing
a different QoS and DS configuration, using a different register to
enable the wm and habing the same UB size for both instances (instead
of a different size between instance 0 and 1).

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2020-10-22 19:47:02 +02:00 committed by Mauro Carvalho Chehab
parent 1786653aa2
commit 40296e712c
2 changed files with 116 additions and 0 deletions
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115
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
View File

@ -133,6 +133,11 @@
#define VFE_0_BUS_BDG_QOS_CFG_7 0x420
#define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa9
#define VFE48_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5
#define VFE48_0_BUS_BDG_QOS_CFG_3_CFG 0xaa55aaa5
#define VFE48_0_BUS_BDG_QOS_CFG_4_CFG 0xaa55aa55
#define VFE48_0_BUS_BDG_QOS_CFG_7_CFG 0x0005aa55
#define VFE_0_BUS_BDG_DS_CFG_0 0x424
#define VFE_0_BUS_BDG_DS_CFG_0_CFG 0xcccc0011
#define VFE_0_BUS_BDG_DS_CFG_1 0x428
@ -153,6 +158,9 @@
#define VFE_0_BUS_BDG_DS_CFG_16 0x464
#define VFE_0_BUS_BDG_DS_CFG_16_CFG 0x40000103
#define VFE48_0_BUS_BDG_DS_CFG_0_CFG 0xcccc1111
#define VFE48_0_BUS_BDG_DS_CFG_16_CFG 0x00000110
#define VFE_0_RDI_CFG_x(x) (0x46c + (0x4 * (x)))
#define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28
#define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28)
@ -231,6 +239,9 @@
#define VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL BIT(3)
#define VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE BIT(4)
#define VFE48_0_BUS_IMAGE_MASTER_CMD 0xcec
#define VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(x) (2 * (x))
#define CAMIF_TIMEOUT_SLEEP_US 1000
#define CAMIF_TIMEOUT_ALL_US 1000000
@ -1139,3 +1150,107 @@ const struct vfe_hw_ops vfe_ops_4_7 = {
.violation_read = vfe_violation_read,
.isr = vfe_isr,
};
static u16 vfe48_get_ub_size(u8 vfe_id)
{
/* On VFE4.8 the ub-size is the same on both instances */
return MSM_VFE_VFE0_UB_SIZE_RDI;
}
static void vfe48_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable)
{
if (enable)
writel_relaxed(2 << VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(wm),
vfe->base + VFE48_0_BUS_IMAGE_MASTER_CMD);
else
writel_relaxed(1 << VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(wm),
vfe->base + VFE48_0_BUS_IMAGE_MASTER_CMD);
/* The WM must be enabled before sending other commands */
wmb();
}
static void vfe48_set_qos(struct vfe_device *vfe)
{
u32 val = VFE48_0_BUS_BDG_QOS_CFG_0_CFG;
u32 val3 = VFE48_0_BUS_BDG_QOS_CFG_3_CFG;
u32 val4 = VFE48_0_BUS_BDG_QOS_CFG_4_CFG;
u32 val7 = VFE48_0_BUS_BDG_QOS_CFG_7_CFG;
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2);
writel_relaxed(val3, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3);
writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4);
writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5);
writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6);
writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);
}
static void vfe48_set_ds(struct vfe_device *vfe)
{
u32 val = VFE48_0_BUS_BDG_DS_CFG_0_CFG;
u32 val16 = VFE48_0_BUS_BDG_DS_CFG_16_CFG;
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14);
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15);
writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16);
}
const struct vfe_hw_ops vfe_ops_4_8 = {
.hw_version_read = vfe_hw_version_read,
.get_ub_size = vfe48_get_ub_size,
.global_reset = vfe_global_reset,
.halt_request = vfe_halt_request,
.halt_clear = vfe_halt_clear,
.wm_enable = vfe48_wm_enable,
.wm_frame_based = vfe_wm_frame_based,
.wm_line_based = vfe_wm_line_based,
.wm_set_framedrop_period = vfe_wm_set_framedrop_period,
.wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern,
.wm_set_ub_cfg = vfe_wm_set_ub_cfg,
.bus_reload_wm = vfe_bus_reload_wm,
.wm_set_ping_addr = vfe_wm_set_ping_addr,
.wm_set_pong_addr = vfe_wm_set_pong_addr,
.wm_get_ping_pong_status = vfe_wm_get_ping_pong_status,
.bus_enable_wr_if = vfe_bus_enable_wr_if,
.bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi,
.wm_set_subsample = vfe_wm_set_subsample,
.bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi,
.set_xbar_cfg = vfe_set_xbar_cfg,
.set_realign_cfg = vfe_set_realign_cfg,
.set_rdi_cid = vfe_set_rdi_cid,
.reg_update = vfe_reg_update,
.reg_update_clear = vfe_reg_update_clear,
.enable_irq_wm_line = vfe_enable_irq_wm_line,
.enable_irq_pix_line = vfe_enable_irq_pix_line,
.enable_irq_common = vfe_enable_irq_common,
.set_demux_cfg = vfe_set_demux_cfg,
.set_scale_cfg = vfe_set_scale_cfg,
.set_crop_cfg = vfe_set_crop_cfg,
.set_clamp_cfg = vfe_set_clamp_cfg,
.set_qos = vfe48_set_qos,
.set_ds = vfe48_set_ds,
.set_cgc_override = vfe_set_cgc_override,
.set_camif_cfg = vfe_set_camif_cfg,
.set_camif_cmd = vfe_set_camif_cmd,
.set_module_cfg = vfe_set_module_cfg,
.camif_wait_for_stop = vfe_camif_wait_for_stop,
.isr_read = vfe_isr_read,
.violation_read = vfe_violation_read,
.isr = vfe_isr,
};

1
drivers/media/platform/qcom/camss/camss-vfe.h
View File

@ -180,5 +180,6 @@ void msm_vfe_get_vfe_line_id(struct media_entity *entity, enum vfe_line_id *id);
extern const struct vfe_hw_ops vfe_ops_4_1;
extern const struct vfe_hw_ops vfe_ops_4_7;
extern const struct vfe_hw_ops vfe_ops_4_8;
#endif /* QC_MSM_CAMSS_VFE_H */