drm/radeon: Move radeon_cursor_move(_locked) to replace forward declaration
No functional change. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer
Alex Deucher
parent
78b1a6010b
commit
3feba08d79
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@ -117,7 +117,115 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
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}
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}
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static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y);
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static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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int xorigin = 0, yorigin = 0;
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int w = radeon_crtc->cursor_width;
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if (ASIC_IS_AVIVO(rdev)) {
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/* avivo cursor are offset into the total surface */
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x += crtc->x;
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y += crtc->y;
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}
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DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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if (x < 0) {
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xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
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x = 0;
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}
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if (y < 0) {
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yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
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y = 0;
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}
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/* fixed on DCE6 and newer */
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if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
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int i = 0;
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struct drm_crtc *crtc_p;
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/*
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* avivo cursor image can't end on 128 pixel boundary or
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* go past the end of the frame if both crtcs are enabled
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*
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* NOTE: It is safe to access crtc->enabled of other crtcs
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* without holding either the mode_config lock or the other
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* crtc's lock as long as write access to this flag _always_
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* grabs all locks.
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*/
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list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
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if (crtc_p->enabled)
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i++;
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}
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if (i > 1) {
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int cursor_end, frame_end;
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cursor_end = x - xorigin + w;
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frame_end = crtc->x + crtc->mode.crtc_hdisplay;
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if (cursor_end >= frame_end) {
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w = w - (cursor_end - frame_end);
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if (!(frame_end & 0x7f))
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w--;
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} else {
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if (!(cursor_end & 0x7f))
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w--;
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}
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if (w <= 0) {
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w = 1;
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cursor_end = x - xorigin + w;
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if (!(cursor_end & 0x7f)) {
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x--;
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WARN_ON_ONCE(x < 0);
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}
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}
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}
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}
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else {
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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y *= 2;
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WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (xorigin << 16)
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| yorigin));
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WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (x << 16)
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| y));
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
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(yorigin * 256)));
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}
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radeon_crtc->cursor_x = x;
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radeon_crtc->cursor_y = y;
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return 0;
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}
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int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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int x, int y)
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{
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int ret;
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radeon_lock_cursor(crtc, true);
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ret = radeon_cursor_move_locked(crtc, x, y);
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radeon_lock_cursor(crtc, false);
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return ret;
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}
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static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
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uint64_t gpu_addr, int hot_x, int hot_y)
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@ -231,113 +339,3 @@ fail:
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return ret;
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}
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static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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int xorigin = 0, yorigin = 0;
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int w = radeon_crtc->cursor_width;
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if (ASIC_IS_AVIVO(rdev)) {
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/* avivo cursor are offset into the total surface */
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x += crtc->x;
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y += crtc->y;
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}
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DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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if (x < 0) {
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xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
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x = 0;
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}
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if (y < 0) {
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yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
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y = 0;
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}
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/* fixed on DCE6 and newer */
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if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
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int i = 0;
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struct drm_crtc *crtc_p;
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/*
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* avivo cursor image can't end on 128 pixel boundary or
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* go past the end of the frame if both crtcs are enabled
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*
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* NOTE: It is safe to access crtc->enabled of other crtcs
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* without holding either the mode_config lock or the other
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* crtc's lock as long as write access to this flag _always_
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* grabs all locks.
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*/
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list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
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if (crtc_p->enabled)
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i++;
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}
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if (i > 1) {
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int cursor_end, frame_end;
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cursor_end = x - xorigin + w;
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frame_end = crtc->x + crtc->mode.crtc_hdisplay;
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if (cursor_end >= frame_end) {
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w = w - (cursor_end - frame_end);
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if (!(frame_end & 0x7f))
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w--;
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} else {
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if (!(cursor_end & 0x7f))
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w--;
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}
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if (w <= 0) {
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w = 1;
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cursor_end = x - xorigin + w;
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if (!(cursor_end & 0x7f)) {
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x--;
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WARN_ON_ONCE(x < 0);
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}
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}
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}
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}
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else {
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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y *= 2;
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WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (xorigin << 16)
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| yorigin));
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WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (x << 16)
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| y));
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
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(yorigin * 256)));
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}
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radeon_crtc->cursor_x = x;
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radeon_crtc->cursor_y = y;
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return 0;
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}
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int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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int x, int y)
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{
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int ret;
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radeon_lock_cursor(crtc, true);
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ret = radeon_cursor_move_locked(crtc, x, y);
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radeon_lock_cursor(crtc, false);
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return ret;
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}
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