[SCSI] fusion - Adding pci recog support for Fibre 949X and 939X chips
* adding pci id support for new Fibre chips, 949X and 939X * adding errata workaround - disabling PIO access except during fwdlb. Signed-off-by: Eric Moore <Eric.Moore@lsil.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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793698ce28
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@ -186,6 +186,26 @@ static void __exit fusion_exit (void);
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#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
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#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
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static void
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pci_disable_io_access(struct pci_dev *pdev)
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{
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u16 command_reg;
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pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
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command_reg &= ~1;
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pci_write_config_word(pdev, PCI_COMMAND, command_reg);
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}
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static void
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pci_enable_io_access(struct pci_dev *pdev)
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{
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u16 command_reg;
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pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
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command_reg |= 1;
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pci_write_config_word(pdev, PCI_COMMAND, command_reg);
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}
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/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
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/*
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* mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
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@ -1161,6 +1181,16 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
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pcixcmd &= 0x8F;
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pci_write_config_byte(pdev, 0x6a, pcixcmd);
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}
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else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC939X) {
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ioc->prod_name = "LSIFC939X";
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ioc->bus_type = FC;
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ioc->errata_flag_1064 = 1;
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}
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else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC949X) {
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ioc->prod_name = "LSIFC949X";
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ioc->bus_type = FC;
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ioc->errata_flag_1064 = 1;
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}
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else if (pdev->device == MPI_MANUFACTPAGE_DEVID_53C1030) {
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ioc->prod_name = "LSI53C1030";
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ioc->bus_type = SCSI;
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@ -1179,6 +1209,9 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
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ioc->bus_type = SCSI;
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}
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if (ioc->errata_flag_1064)
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pci_disable_io_access(pdev);
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sprintf(ioc->name, "ioc%d", ioc->id);
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spin_lock_init(&ioc->FreeQlock);
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@ -2667,7 +2700,7 @@ mpt_downloadboot(MPT_ADAPTER *ioc, int sleepFlag)
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/* prevent a second downloadboot and memory free with alt_ioc */
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if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
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ioc->alt_ioc->cached_fw = NULL;
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CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
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CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
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CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
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@ -2725,6 +2758,9 @@ mpt_downloadboot(MPT_ADAPTER *ioc, int sleepFlag)
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/* Write the LoadStartAddress to the DiagRw Address Register
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* using Programmed IO
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*/
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if (ioc->errata_flag_1064)
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pci_enable_io_access(ioc->pcidev);
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CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
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ddlprintk((MYIOC_s_INFO_FMT "LoadStart addr written 0x%x \n",
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ioc->name, pFwHeader->LoadStartAddress));
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@ -2771,6 +2807,9 @@ mpt_downloadboot(MPT_ADAPTER *ioc, int sleepFlag)
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CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
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CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
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if (ioc->errata_flag_1064)
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pci_disable_io_access(ioc->pcidev);
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diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
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ddlprintk((MYIOC_s_INFO_FMT "downloadboot diag0val=%x, turning off PREVENT_IOC_BOOT, DISABLE_ARM\n",
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ioc->name, diag0val));
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@ -562,6 +562,13 @@ typedef struct _MPT_ADAPTER
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FCPortPage0_t fc_port_page0[2];
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LANPage0_t lan_cnfg_page0;
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LANPage1_t lan_cnfg_page1;
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/*
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* Description: errata_flag_1064
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* If a PCIX read occurs within 1 or 2 cycles after the chip receives
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* a split completion for a read data, an internal address pointer incorrectly
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* increments by 32 bytes
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*/
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int errata_flag_1064;
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u8 FirstWhoInit;
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u8 upload_fw; /* If set, do a fw upload */
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u8 reload_fw; /* Force a FW Reload on next reset */
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@ -134,6 +134,10 @@ static struct pci_device_id mptfc_pci_table[] = {
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PCI_ANY_ID, PCI_ANY_ID },
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{ PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_FC929X,
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PCI_ANY_ID, PCI_ANY_ID },
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{ PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_FC939X,
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PCI_ANY_ID, PCI_ANY_ID },
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{ PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_FC949X,
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PCI_ANY_ID, PCI_ANY_ID },
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{0} /* Terminating entry */
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};
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MODULE_DEVICE_TABLE(pci, mptfc_pci_table);
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