drm/amdgpu: enable smart shift on dGPU (v5)
enable smart shift on dGPU if it is part of HG system and the platform supports ATCS method to handle power shift. V2: avoid psc updates in baco enter and exit (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling. (Alex) V4: check for return value and warn on failed update (Shashank) return 0 if device does not support smart shift. (Lizo) V5: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -130,6 +130,13 @@ struct amdgpu_mgpu_info
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bool pending_reset;
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};
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enum amdgpu_ss {
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AMDGPU_SS_DRV_LOAD,
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AMDGPU_SS_DEV_D0,
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AMDGPU_SS_DEV_D3,
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AMDGPU_SS_DRV_UNLOAD
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};
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struct amdgpu_watchdog_timer
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{
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bool timeout_fatal_disable;
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@ -1264,6 +1271,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
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bool amdgpu_device_supports_atpx(struct drm_device *dev);
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bool amdgpu_device_supports_px(struct drm_device *dev);
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bool amdgpu_device_supports_boco(struct drm_device *dev);
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bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
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bool amdgpu_device_supports_baco(struct drm_device *dev);
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bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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@ -1336,6 +1344,13 @@ struct amdgpu_afmt_acr {
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struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
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/* amdgpu_acpi.c */
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/* ATCS Device/Driver State */
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#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
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#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
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#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
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#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
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#if defined(CONFIG_ACPI)
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int amdgpu_acpi_init(struct amdgpu_device *adev);
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void amdgpu_acpi_fini(struct amdgpu_device *adev);
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@ -1345,6 +1360,7 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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u8 perf_req, bool advertise);
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int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state);
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int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
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int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
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void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
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@ -1358,6 +1374,8 @@ static inline void amdgpu_acpi_detect(void) { }
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static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
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static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state) { return 0; }
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static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
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enum amdgpu_ss ss_state) { return 0; }
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#endif
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int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
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@ -754,6 +754,55 @@ int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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return 0;
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}
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/**
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* amdgpu_acpi_smart_shift_update - update dGPU device state to SBIOS
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*
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* @dev: drm_device pointer
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* @ss_state: current smart shift event
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*
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* returns 0 on success,
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* otherwise return error number.
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*/
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int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state)
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{
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struct amdgpu_device *adev = drm_to_adev(dev);
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int r;
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if (!amdgpu_device_supports_smart_shift(dev))
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return 0;
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switch (ss_state) {
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/* SBIOS trigger “stop”, “enable” and “start” at D0, Driver Operational.
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* SBIOS trigger “stop” at D3, Driver Not Operational.
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* SBIOS trigger “stop” and “disable” at D0, Driver NOT operational.
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*/
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case AMDGPU_SS_DRV_LOAD:
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r = amdgpu_acpi_power_shift_control(adev,
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AMDGPU_ATCS_PSC_DEV_STATE_D0,
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AMDGPU_ATCS_PSC_DRV_STATE_OPR);
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break;
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case AMDGPU_SS_DEV_D0:
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r = amdgpu_acpi_power_shift_control(adev,
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AMDGPU_ATCS_PSC_DEV_STATE_D0,
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AMDGPU_ATCS_PSC_DRV_STATE_OPR);
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break;
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case AMDGPU_SS_DEV_D3:
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r = amdgpu_acpi_power_shift_control(adev,
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AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT,
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AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR);
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break;
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case AMDGPU_SS_DRV_UNLOAD:
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r = amdgpu_acpi_power_shift_control(adev,
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AMDGPU_ATCS_PSC_DEV_STATE_D0,
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AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR);
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break;
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default:
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return -EINVAL;
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}
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return r;
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}
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/**
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* amdgpu_acpi_event - handle notify events
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*
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@ -263,6 +263,21 @@ bool amdgpu_device_supports_baco(struct drm_device *dev)
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return amdgpu_asic_supports_baco(adev);
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}
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/**
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* amdgpu_device_supports_smart_shift - Is the device dGPU with
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* smart shift support
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*
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* @dev: drm_device pointer
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*
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* Returns true if the device is a dGPU with Smart Shift support,
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* otherwise returns false.
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*/
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bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
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{
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return (amdgpu_device_supports_boco(dev) &&
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amdgpu_acpi_is_power_shift_control_supported());
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}
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/*
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* VRAM access helper functions
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*/
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@ -3750,6 +3765,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
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return 0;
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adev->in_suspend = true;
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if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
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DRM_WARN("smart shift update failed\n");
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drm_kms_helper_poll_disable(dev);
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if (fbcon)
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@ -3859,6 +3878,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
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#endif
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adev->in_suspend = false;
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if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
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DRM_WARN("smart shift update failed\n");
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return 0;
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}
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@ -4938,6 +4960,8 @@ skip_hw_reset:
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amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
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} else {
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dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
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if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
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DRM_WARN("smart shift update failed\n");
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}
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}
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@ -91,6 +91,9 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)
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pm_runtime_forbid(dev->dev);
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}
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if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
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DRM_WARN("smart shift update failed\n");
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amdgpu_acpi_fini(adev);
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amdgpu_device_fini(adev);
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}
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@ -214,6 +217,9 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
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pm_runtime_put_autosuspend(dev->dev);
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}
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if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
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DRM_WARN("smart shift update failed\n");
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out:
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if (r) {
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/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
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