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arm64: dts: renesas: r8a774b1: Add CAN and CAN FD support 

Add CAN and CAN FD support to the RZ/G2N SoC specific dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1570717560-7431-4-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Fabrizio Castro 2019-10-10 15:26:00 +01:00 committed by Geert Uytterhoeven
parent 8292f5eb38
commit 3fa08cbb06
1 changed files with 45 additions and 3 deletions
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48
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
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@ -994,18 +994,60 @@
}; };
can0: can@e6c30000 { can0: can@e6c30000 {
compatible = "renesas,can-r8a774b1",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>; reg = <0 0xe6c30000 0 0x1000>;
/* placeholder */ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
}; };
can1: can@e6c38000 { can1: can@e6c38000 {
compatible = "renesas,can-r8a774b1",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>; reg = <0 0xe6c38000 0 0x1000>;
/* placeholder */ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
}; };
canfd: can@e66c0000 { canfd: can@e66c0000 {
compatible = "renesas,r8a774b1-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>; reg = <0 0xe66c0000 0 0x8000>;
/* placeholder */ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
}; };
pwm0: pwm@e6e30000 { pwm0: pwm@e6e30000 {