arm64: dts: renesas: r8a774b1: Add CAN and CAN FD support
Add CAN and CAN FD support to the RZ/G2N SoC specific dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Link: https://lore.kernel.org/r/1570717560-7431-4-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -994,18 +994,60 @@
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};
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can0: can@e6c30000 {
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compatible = "renesas,can-r8a774b1",
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"renesas,rcar-gen3-can";
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reg = <0 0xe6c30000 0 0x1000>;
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/* placeholder */
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 916>,
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<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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status = "disabled";
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};
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can1: can@e6c38000 {
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compatible = "renesas,can-r8a774b1",
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"renesas,rcar-gen3-can";
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reg = <0 0xe6c38000 0 0x1000>;
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/* placeholder */
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 915>,
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<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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status = "disabled";
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};
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canfd: can@e66c0000 {
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compatible = "renesas,r8a774b1-canfd",
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"renesas,rcar-gen3-canfd";
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reg = <0 0xe66c0000 0 0x8000>;
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/* placeholder */
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 914>,
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<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
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<&can_clk>;
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clock-names = "fck", "canfd", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 914>;
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status = "disabled";
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channel0 {
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status = "disabled";
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};
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channel1 {
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status = "disabled";
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};
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};
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pwm0: pwm@e6e30000 {
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