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RISC-V: Clear SIP bit only when using SBI IPI operations 

The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230328035223.1480939-2-apatel@ventanamicro.com
This commit is contained in:
Anup Patel 2023-03-28 09:22:17 +05:30 committed by Marc Zyngier
parent 197b6b60ae
commit 3ee92565b8
2 changed files with 7 additions and 3 deletions
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8
arch/riscv/kernel/sbi.c
View File

@ -646,8 +646,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
sbi_send_ipi(target);
}
static void sbi_ipi_clear(void)
{
csr_clear(CSR_IP, IE_SIE);
}
static const struct riscv_ipi_ops sbi_ipi_ops = {
.ipi_inject = sbi_send_cpumask_ipi
.ipi_inject = sbi_send_cpumask_ipi,
.ipi_clear = sbi_ipi_clear
};
void __init sbi_init(void)

2
arch/riscv/kernel/smp.c
View File

@ -112,8 +112,6 @@ void riscv_clear_ipi(void)
{
if (ipi_ops && ipi_ops->ipi_clear)
ipi_ops->ipi_clear();
csr_clear(CSR_IP, IE_SIE);
}
EXPORT_SYMBOL_GPL(riscv_clear_ipi);