usb: musb: introduce DA8xx/OMAP-L1x glue layer
Texas Instruments DA8xx/OMAP-L1x glue layer for the MUSBMHRDC driver. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Yadviga Grigorieva <yadviga@ru.mvista.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Sergei Shtylyov
Greg Kroah-Hartman
parent
d613746d8b
commit
3ee076dea6
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@ -45,6 +45,9 @@ config USB_MUSB_SOC
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comment "DaVinci 35x and 644x USB support"
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comment "DaVinci 35x and 644x USB support"
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depends on USB_MUSB_HDRC && ARCH_DAVINCI_DMx
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depends on USB_MUSB_HDRC && ARCH_DAVINCI_DMx
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comment "DA8xx/OMAP-L1x USB support"
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depends on USB_MUSB_HDRC && ARCH_DAVINCI_DA8XX
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comment "OMAP 243x high speed USB support"
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comment "OMAP 243x high speed USB support"
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depends on USB_MUSB_HDRC && ARCH_OMAP2430
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depends on USB_MUSB_HDRC && ARCH_OMAP2430
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@ -144,7 +147,7 @@ config USB_MUSB_HDRC_HCD
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config MUSB_PIO_ONLY
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config MUSB_PIO_ONLY
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bool 'Disable DMA (always use PIO)'
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bool 'Disable DMA (always use PIO)'
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depends on USB_MUSB_HDRC
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depends on USB_MUSB_HDRC
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default y if USB_TUSB6010
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default USB_TUSB6010 || ARCH_DAVINCI_DA8XX
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help
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help
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All data is copied between memory and FIFO by the CPU.
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All data is copied between memory and FIFO by the CPU.
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DMA controllers are ignored.
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DMA controllers are ignored.
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@ -10,6 +10,10 @@ ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
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musb_hdrc-objs += davinci.o
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musb_hdrc-objs += davinci.o
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endif
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endif
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ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y)
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musb_hdrc-objs += da8xx.o
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endif
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ifeq ($(CONFIG_USB_TUSB6010),y)
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ifeq ($(CONFIG_USB_TUSB6010),y)
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musb_hdrc-objs += tusb6010.o
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musb_hdrc-objs += tusb6010.o
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endif
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endif
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@ -0,0 +1,469 @@
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/*
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* Texas Instruments DA8xx/OMAP-L1x "glue layer"
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*
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* Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
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*
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* Based on the DaVinci "glue layer" code.
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/da8xx.h>
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#include <mach/usb.h>
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#include "musb_core.h"
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/*
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* DA8XX specific definitions
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*/
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/* USB 2.0 OTG module registers */
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#define DA8XX_USB_REVISION_REG 0x00
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#define DA8XX_USB_CTRL_REG 0x04
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#define DA8XX_USB_STAT_REG 0x08
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#define DA8XX_USB_EMULATION_REG 0x0c
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#define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
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#define DA8XX_USB_AUTOREQ_REG 0x14
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#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
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#define DA8XX_USB_TEARDOWN_REG 0x1c
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#define DA8XX_USB_INTR_SRC_REG 0x20
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#define DA8XX_USB_INTR_SRC_SET_REG 0x24
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#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
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#define DA8XX_USB_INTR_MASK_REG 0x2c
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#define DA8XX_USB_INTR_MASK_SET_REG 0x30
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#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
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#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
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#define DA8XX_USB_END_OF_INTR_REG 0x3c
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#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
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/* Control register bits */
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#define DA8XX_SOFT_RESET_MASK 1
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#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
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#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
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/* USB interrupt register bits */
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#define DA8XX_INTR_USB_SHIFT 16
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#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
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/* interrupts and DRVVBUS interrupt */
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#define DA8XX_INTR_DRVVBUS 0x100
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#define DA8XX_INTR_RX_SHIFT 8
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#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
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#define DA8XX_INTR_TX_SHIFT 0
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#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
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#define DA8XX_MENTOR_CORE_OFFSET 0x400
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#define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
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/*
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* REVISIT (PM): we should be able to keep the PHY in low power mode most
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* of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
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* and, when in host mode, autosuspending idle root ports... PHY_PLLON
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* (overriding SUSPENDM?) then likely needs to stay off.
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*/
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static inline void phy_on(void)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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/*
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* Start the on-chip PHY and its PLL.
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*/
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cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
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cfgchip2 |= CFGCHIP2_PHY_PLLON;
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__raw_writel(cfgchip2, CFGCHIP2);
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pr_info("Waiting for USB PHY clock good...\n");
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while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
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cpu_relax();
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}
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static inline void phy_off(void)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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/*
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* Ensure that USB 1.1 reference clock is not being sourced from
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* USB 2.0 PHY. Otherwise do not power down the PHY.
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*/
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if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
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(cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
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pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
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"can't power it down\n");
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return;
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}
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/*
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* Power down the on-chip PHY.
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*/
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cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
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__raw_writel(cfgchip2, CFGCHIP2);
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}
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/*
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* Because we don't set CTRL.UINT, it's "important" to:
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* - not read/write INTRUSB/INTRUSBE (except during
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* initial setup, as a workaround);
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* - use INTSET/INTCLR instead.
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*/
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/**
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* musb_platform_enable - enable interrupts
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*/
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void musb_platform_enable(struct musb *musb)
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{
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void __iomem *reg_base = musb->ctrl_base;
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u32 mask;
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/* Workaround: setup IRQs through both register sets. */
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mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
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((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
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DA8XX_INTR_USB_MASK;
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musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
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/* Force the DRVVBUS IRQ so we can start polling for ID change. */
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if (is_otg_enabled(musb))
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musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
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DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
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}
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/**
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* musb_platform_disable - disable HDRC and flush interrupts
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*/
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void musb_platform_disable(struct musb *musb)
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{
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void __iomem *reg_base = musb->ctrl_base;
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musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
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DA8XX_INTR_USB_MASK |
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DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
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}
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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#define portstate(stmt) stmt
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#else
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#define portstate(stmt)
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#endif
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static void da8xx_set_vbus(struct musb *musb, int is_on)
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{
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WARN_ON(is_on && is_peripheral_active(musb));
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}
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#define POLL_SECONDS 2
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static struct timer_list otg_workaround;
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static void otg_timer(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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void __iomem *mregs = musb->mregs;
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u8 devctl;
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unsigned long flags;
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/*
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* We poll because DaVinci's won't expose several OTG-critical
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* status change events (from the transceiver) otherwise.
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*/
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->state) {
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case OTG_STATE_A_WAIT_BCON:
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devctl &= ~MUSB_DEVCTL_SESSION;
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musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE) {
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musb->xceiv->state = OTG_STATE_B_IDLE;
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MUSB_DEV_MODE(musb);
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} else {
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musb->xceiv->state = OTG_STATE_A_IDLE;
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MUSB_HST_MODE(musb);
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}
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break;
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case OTG_STATE_A_WAIT_VFALL:
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/*
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* Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
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* RTL seems to mis-handle session "start" otherwise (or in
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* our case "recover"), in routine "VBUS was valid by the time
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* VBUSERR got reported during enumeration" cases.
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*/
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if (devctl & MUSB_DEVCTL_VBUS) {
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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break;
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}
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musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
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musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
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MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
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break;
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case OTG_STATE_B_IDLE:
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if (!is_peripheral_enabled(musb))
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break;
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/*
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* There's no ID-changed IRQ, so we have no good way to tell
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* when to switch to the A-Default state machine (by setting
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* the DEVCTL.Session bit).
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*
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* Workaround: whenever we're in B_IDLE, try setting the
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* session flag every few seconds. If it works, ID was
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* grounded and we're now in the A-Default state machine.
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*
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* NOTE: setting the session flag is _supposed_ to trigger
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* SRP but clearly it doesn't.
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*/
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musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE)
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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else
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musb->xceiv->state = OTG_STATE_A_IDLE;
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break;
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default:
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
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{
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static unsigned long last_timer;
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if (!is_otg_enabled(musb))
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return;
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if (timeout == 0)
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timeout = jiffies + msecs_to_jiffies(3);
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/* Never idle if active, or when VBUS timeout is not set as host */
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if (musb->is_active || (musb->a_wait_bcon == 0 &&
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musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
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DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
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del_timer(&otg_workaround);
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last_timer = jiffies;
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return;
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}
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if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
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DBG(4, "Longer idle timer already pending, ignoring...\n");
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return;
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}
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last_timer = timeout;
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DBG(4, "%s inactive, starting idle timer for %u ms\n",
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otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
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mod_timer(&otg_workaround, timeout);
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}
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static irqreturn_t da8xx_interrupt(int irq, void *hci)
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{
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struct musb *musb = hci;
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void __iomem *reg_base = musb->ctrl_base;
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unsigned long flags;
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irqreturn_t ret = IRQ_NONE;
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u32 status;
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spin_lock_irqsave(&musb->lock, flags);
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/*
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* NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
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* the Mentor registers (except for setup), use the TI ones and EOI.
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*/
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/* Acknowledge and handle non-CPPI interrupts */
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status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
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if (!status)
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goto eoi;
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musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
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DBG(4, "USB IRQ %08x\n", status);
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||||||
|
musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
|
||||||
|
musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
|
||||||
|
musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
|
||||||
|
* DA8xx's missing ID change IRQ. We need an ID change IRQ to
|
||||||
|
* switch appropriately between halves of the OTG state machine.
|
||||||
|
* Managing DEVCTL.Session per Mentor docs requires that we know its
|
||||||
|
* value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
|
||||||
|
* Also, DRVVBUS pulses for SRP (but not at 5 V)...
|
||||||
|
*/
|
||||||
|
if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
|
||||||
|
int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
|
||||||
|
void __iomem *mregs = musb->mregs;
|
||||||
|
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
|
||||||
|
int err;
|
||||||
|
|
||||||
|
err = is_host_enabled(musb) && (musb->int_usb &
|
||||||
|
MUSB_INTR_VBUSERROR);
|
||||||
|
if (err) {
|
||||||
|
/*
|
||||||
|
* The Mentor core doesn't debounce VBUS as needed
|
||||||
|
* to cope with device connect current spikes. This
|
||||||
|
* means it's not uncommon for bus-powered devices
|
||||||
|
* to get VBUS errors during enumeration.
|
||||||
|
*
|
||||||
|
* This is a workaround, but newer RTL from Mentor
|
||||||
|
* seems to allow a better one: "re"-starting sessions
|
||||||
|
* without waiting for VBUS to stop registering in
|
||||||
|
* devctl.
|
||||||
|
*/
|
||||||
|
musb->int_usb &= ~MUSB_INTR_VBUSERROR;
|
||||||
|
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
|
||||||
|
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
|
||||||
|
WARNING("VBUS error workaround (delay coming)\n");
|
||||||
|
} else if (is_host_enabled(musb) && drvvbus) {
|
||||||
|
MUSB_HST_MODE(musb);
|
||||||
|
musb->xceiv->default_a = 1;
|
||||||
|
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
|
||||||
|
portstate(musb->port1_status |= USB_PORT_STAT_POWER);
|
||||||
|
del_timer(&otg_workaround);
|
||||||
|
} else {
|
||||||
|
musb->is_active = 0;
|
||||||
|
MUSB_DEV_MODE(musb);
|
||||||
|
musb->xceiv->default_a = 0;
|
||||||
|
musb->xceiv->state = OTG_STATE_B_IDLE;
|
||||||
|
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
|
||||||
|
}
|
||||||
|
|
||||||
|
DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
|
||||||
|
drvvbus ? "on" : "off",
|
||||||
|
otg_state_string(musb),
|
||||||
|
err ? " ERROR" : "",
|
||||||
|
devctl);
|
||||||
|
ret = IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (musb->int_tx || musb->int_rx || musb->int_usb)
|
||||||
|
ret |= musb_interrupt(musb);
|
||||||
|
|
||||||
|
eoi:
|
||||||
|
/* EOI needs to be written for the IRQ to be re-asserted. */
|
||||||
|
if (ret == IRQ_HANDLED || status)
|
||||||
|
musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
|
||||||
|
|
||||||
|
/* Poll for ID change */
|
||||||
|
if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
|
||||||
|
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&musb->lock, flags);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
|
||||||
|
{
|
||||||
|
u32 cfgchip2 = __raw_readl(CFGCHIP2);
|
||||||
|
|
||||||
|
cfgchip2 &= ~CFGCHIP2_OTGMODE;
|
||||||
|
switch (musb_mode) {
|
||||||
|
#ifdef CONFIG_USB_MUSB_HDRC_HCD
|
||||||
|
case MUSB_HOST: /* Force VBUS valid, ID = 0 */
|
||||||
|
cfgchip2 |= CFGCHIP2_FORCE_HOST;
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
|
||||||
|
case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
|
||||||
|
cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_USB_MUSB_OTG
|
||||||
|
case MUSB_OTG: /* Don't override the VBUS/ID comparators */
|
||||||
|
cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
default:
|
||||||
|
DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
|
||||||
|
}
|
||||||
|
|
||||||
|
__raw_writel(cfgchip2, CFGCHIP2);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int __init musb_platform_init(struct musb *musb, void *board_data)
|
||||||
|
{
|
||||||
|
void __iomem *reg_base = musb->ctrl_base;
|
||||||
|
u32 rev;
|
||||||
|
|
||||||
|
musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
|
||||||
|
|
||||||
|
clk_enable(musb->clock);
|
||||||
|
|
||||||
|
/* Returns zero if e.g. not clocked */
|
||||||
|
rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
|
||||||
|
if (!rev)
|
||||||
|
goto fail;
|
||||||
|
|
||||||
|
usb_nop_xceiv_register();
|
||||||
|
musb->xceiv = otg_get_transceiver();
|
||||||
|
if (!musb->xceiv)
|
||||||
|
goto fail;
|
||||||
|
|
||||||
|
if (is_host_enabled(musb))
|
||||||
|
setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
|
||||||
|
|
||||||
|
musb->board_set_vbus = da8xx_set_vbus;
|
||||||
|
|
||||||
|
/* Reset the controller */
|
||||||
|
musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
|
||||||
|
|
||||||
|
/* Start the on-chip PHY and its PLL. */
|
||||||
|
phy_on();
|
||||||
|
|
||||||
|
msleep(5);
|
||||||
|
|
||||||
|
/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
|
||||||
|
pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
|
||||||
|
rev, __raw_readl(CFGCHIP2),
|
||||||
|
musb_readb(reg_base, DA8XX_USB_CTRL_REG));
|
||||||
|
|
||||||
|
musb->isr = da8xx_interrupt;
|
||||||
|
return 0;
|
||||||
|
fail:
|
||||||
|
clk_disable(musb->clock);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
int musb_platform_exit(struct musb *musb)
|
||||||
|
{
|
||||||
|
if (is_host_enabled(musb))
|
||||||
|
del_timer_sync(&otg_workaround);
|
||||||
|
|
||||||
|
phy_off();
|
||||||
|
|
||||||
|
otg_put_transceiver(musb->xceiv);
|
||||||
|
usb_nop_xceiv_unregister();
|
||||||
|
|
||||||
|
clk_disable(musb->clock);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
@ -599,6 +599,7 @@ extern void musb_hnp_stop(struct musb *musb);
|
||||||
extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
|
extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
|
||||||
|
|
||||||
#if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
|
#if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
|
||||||
|
defined(CONFIG_ARCH_DAVINCI_DA8XX) || \
|
||||||
defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
|
defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
|
||||||
defined(CONFIG_ARCH_OMAP4)
|
defined(CONFIG_ARCH_OMAP4)
|
||||||
extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
|
extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue