drivers: memory: Introduce Marvell EBU Device Bus driver
Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ezequiel Garcia
Greg Kroah-Hartman
parent
ced9017a4f
commit
3edad321b1
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@ -0,0 +1,156 @@
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Device tree bindings for MVEBU Device Bus controllers
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The Device Bus controller available in some Marvell's SoC allows to control
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different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
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The actual devices are instantiated from the child nodes of a Device Bus node.
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Required properties:
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- compatible: Currently only Armada 370/XP SoC are supported,
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with this compatible string:
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marvell,mvebu-devbus
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- reg: A resource specifier for the register space.
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This is the base address of a chip select within
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the controller's register space.
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(see the example below)
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- #address-cells: Must be set to 1
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- #size-cells: Must be set to 1
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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0 <physical address of mapping> <size>
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Mandatory timing properties for child nodes:
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Read parameters:
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- devbus,turn-off-ps: Defines the time during which the controller does not
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drive the AD bus after the completion of a device read.
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This prevents contentions on the Device Bus after a read
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cycle from a slow device.
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- devbus,bus-width: Defines the bus width (e.g. <16>)
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- devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
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to read data sample. This parameter is useful for
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synchronous pipelined devices, where the address
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precedes the read data by one or two cycles.
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- devbus,acc-first-ps: Defines the time delay from the negation of
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ALE[0] to the cycle that the first read data is sampled
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by the controller.
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- devbus,acc-next-ps: Defines the time delay between the cycle that
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samples data N and the cycle that samples data N+1
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(in burst accesses).
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- devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
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DEV_OEn assertion. If set to 0 (default),
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DEV_OEn and DEV_CSn are asserted at the same cycle.
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This parameter has no affect on <acc-first-ps> parameter
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(no affect on first data sample). Set <rd-setup-ps>
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to a value smaller than <acc-first-ps>.
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- devbus,rd-hold-ps: Defines the time between the last data sample to the
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de-assertion of DEV_CSn. If set to 0 (default),
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DEV_OEn and DEV_CSn are de-asserted at the same cycle
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(the cycle of the last data sample).
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This parameter has no affect on DEV_OEn de-assertion.
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DEV_OEn is always de-asserted the next cycle after
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last data sampled. Also this parameter has no
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affect on <turn-off-ps> parameter.
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Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
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Write parameters:
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- devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
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to the DEV_WEn assertion.
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- devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
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A[2:0] and Data are kept valid as long as DEV_WEn
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is active. This parameter defines the setup time of
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address and data to DEV_WEn rise.
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- devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
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inactive (high) between data beats of a burst write.
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DEV_A[2:0] and Data are kept valid (do not toggle) for
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<wr-high-ps> - <tick> ps.
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This parameter defines the hold time of address and
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data after DEV_WEn rise.
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- devbus,sync-enable: Synchronous device enable.
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1: True
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0: False
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An example for an Armada XP GP board, with a 16 MiB NOR device as child
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is showed below. Note that the Device Bus driver is in charge of allocating
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the mbus address decoding window for each of its child devices.
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The window is created using the chip select specified in the child
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device node together with the base address and size specified in the ranges
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property. For instance, in the example below the allocated decoding window
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will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
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for chip select 0 (a.k.a DEV_BOOTCS).
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This address window handling is done in this mvebu-devbus only as a temporary
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solution. It will be removed when the support for mbus device tree binding is
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added.
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The reg property implicitly specifies the chip select as this:
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0x10400: DEV_BOOTCS
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0x10408: DEV_CS0
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0x10410: DEV_CS1
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0x10418: DEV_CS2
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0x10420: DEV_CS3
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Example:
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devbus-bootcs@d0010400 {
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status = "okay";
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ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
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#address-cells = <1>;
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#size-cells = <1>;
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/* Device Bus parameters are required */
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/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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flash@0 {
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compatible = "cfi-flash";
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/* 16 MiB */
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reg = <0 0x1000000>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* We split the 16 MiB in two partitions,
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* just as an example.
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*/
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partition@0 {
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label = "First";
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reg = <0 0x800000>;
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};
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partition@800000 {
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label = "Second";
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reg = <0x800000 0x800000>;
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};
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};
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};
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@ -20,6 +20,16 @@ config TI_EMIF
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parameters and other settings during frequency, voltage and
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temperature changes
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config MVEBU_DEVBUS
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bool "Marvell EBU Device Bus Controller"
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default y
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depends on PLAT_ORION && OF
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help
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This driver is for the Device Bus controller available in some
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Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
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Armada 370 and Armada XP. This controller allows to handle flash
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devices such as NOR, NAND, SRAM, and FPGA.
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config TEGRA20_MC
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bool "Tegra20 Memory Controller(MC) driver"
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default y
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@ -6,5 +6,6 @@ ifeq ($(CONFIG_DDR),y)
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obj-$(CONFIG_OF) += of_memory.o
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endif
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obj-$(CONFIG_TI_EMIF) += emif.o
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obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
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obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
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obj-$(CONFIG_TEGRA30_MC) += tegra30-mc.o
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@ -0,0 +1,340 @@
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/*
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* Marvell EBU SoC Device Bus Controller
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* (memory controller for NOR/NAND/SRAM/FPGA devices)
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*
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* Copyright (C) 2013 Marvell
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/mbus.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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/* Register definitions */
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#define DEV_WIDTH_BIT 30
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#define BADR_SKEW_BIT 28
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#define RD_HOLD_BIT 23
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#define ACC_NEXT_BIT 17
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#define RD_SETUP_BIT 12
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#define ACC_FIRST_BIT 6
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#define SYNC_ENABLE_BIT 24
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#define WR_HIGH_BIT 16
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#define WR_LOW_BIT 8
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#define READ_PARAM_OFFSET 0x0
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#define WRITE_PARAM_OFFSET 0x4
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static const char * const devbus_wins[] = {
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"devbus-boot",
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"devbus-cs0",
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"devbus-cs1",
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"devbus-cs2",
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"devbus-cs3",
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};
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struct devbus_read_params {
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u32 bus_width;
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u32 badr_skew;
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u32 turn_off;
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u32 acc_first;
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u32 acc_next;
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u32 rd_setup;
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u32 rd_hold;
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};
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struct devbus_write_params {
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u32 sync_enable;
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u32 wr_high;
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u32 wr_low;
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u32 ale_wr;
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};
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struct devbus {
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struct device *dev;
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void __iomem *base;
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unsigned long tick_ps;
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};
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static int get_timing_param_ps(struct devbus *devbus,
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struct device_node *node,
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const char *name,
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u32 *ticks)
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{
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u32 time_ps;
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int err;
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err = of_property_read_u32(node, name, &time_ps);
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if (err < 0) {
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dev_err(devbus->dev, "%s has no '%s' property\n",
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name, node->full_name);
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return err;
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}
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*ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
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dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
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name, time_ps, *ticks);
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return 0;
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}
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static int devbus_set_timing_params(struct devbus *devbus,
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struct device_node *node)
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{
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struct devbus_read_params r;
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struct devbus_write_params w;
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u32 value;
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int err;
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dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
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devbus->tick_ps);
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/* Get read timings */
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err = of_property_read_u32(node, "devbus,bus-width", &r.bus_width);
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if (err < 0) {
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dev_err(devbus->dev,
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"%s has no 'devbus,bus-width' property\n",
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node->full_name);
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return err;
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}
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/* Convert bit width to byte width */
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r.bus_width /= 8;
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err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
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&r.badr_skew);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
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&r.turn_off);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
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&r.acc_first);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
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&r.acc_next);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
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&r.rd_setup);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
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&r.rd_hold);
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if (err < 0)
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return err;
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/* Get write timings */
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err = of_property_read_u32(node, "devbus,sync-enable",
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&w.sync_enable);
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if (err < 0) {
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dev_err(devbus->dev,
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"%s has no 'devbus,sync-enable' property\n",
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node->full_name);
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return err;
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}
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err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
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&w.ale_wr);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
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&w.wr_low);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
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&w.wr_high);
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if (err < 0)
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return err;
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/* Set read timings */
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value = r.bus_width << DEV_WIDTH_BIT |
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r.badr_skew << BADR_SKEW_BIT |
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r.rd_hold << RD_HOLD_BIT |
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r.acc_next << ACC_NEXT_BIT |
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r.rd_setup << RD_SETUP_BIT |
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r.acc_first << ACC_FIRST_BIT |
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r.turn_off;
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dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
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devbus->base + READ_PARAM_OFFSET,
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value);
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writel(value, devbus->base + READ_PARAM_OFFSET);
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/* Set write timings */
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value = w.sync_enable << SYNC_ENABLE_BIT |
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w.wr_low << WR_LOW_BIT |
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w.wr_high << WR_HIGH_BIT |
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w.ale_wr;
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dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
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devbus->base + WRITE_PARAM_OFFSET,
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value);
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writel(value, devbus->base + WRITE_PARAM_OFFSET);
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return 0;
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}
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static int mvebu_devbus_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct device_node *parent;
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struct devbus *devbus;
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struct resource *res;
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struct clk *clk;
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unsigned long rate;
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const __be32 *ranges;
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int err, cs;
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int addr_cells, p_addr_cells, size_cells;
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int ranges_len, tuple_len;
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u32 base, size;
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devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
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if (!devbus)
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return -ENOMEM;
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devbus->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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devbus->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(devbus->base))
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return PTR_ERR(devbus->base);
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clk_prepare_enable(clk);
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/*
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* Obtain clock period in picoseconds,
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* we need this in order to convert timing
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* parameters from cycles to picoseconds.
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*/
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rate = clk_get_rate(clk) / 1000;
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devbus->tick_ps = 1000000000 / rate;
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/* Read the device tree node and set the new timing parameters */
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err = devbus_set_timing_params(devbus, node);
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if (err < 0)
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return err;
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/*
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* Allocate an address window for this device.
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* If the device probing fails, then we won't be able to
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* remove the allocated address decoding window.
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*
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* FIXME: This is only a temporary hack! We need to do this here
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* because we still don't have device tree bindings for mbus.
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* Once that support is added, we will declare these address windows
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* statically in the device tree, and remove the window configuration
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* from here.
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*/
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/*
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* Get the CS to choose the window string.
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* This is a bit hacky, but it will be removed once the
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* address windows are declared in the device tree.
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*/
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cs = (((unsigned long)devbus->base) % 0x400) / 8;
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/*
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* Parse 'ranges' property to obtain a (base,size) window tuple.
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* This will be removed once the address windows
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* are declared in the device tree.
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*/
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parent = of_get_parent(node);
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if (!parent)
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return -EINVAL;
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p_addr_cells = of_n_addr_cells(parent);
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of_node_put(parent);
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|
||||
addr_cells = of_n_addr_cells(node);
|
||||
size_cells = of_n_size_cells(node);
|
||||
tuple_len = (p_addr_cells + addr_cells + size_cells) * sizeof(__be32);
|
||||
|
||||
ranges = of_get_property(node, "ranges", &ranges_len);
|
||||
if (ranges == NULL || ranges_len != tuple_len)
|
||||
return -EINVAL;
|
||||
|
||||
base = of_translate_address(node, ranges + addr_cells);
|
||||
if (base == OF_BAD_ADDR)
|
||||
return -EINVAL;
|
||||
size = of_read_number(ranges + addr_cells + p_addr_cells, size_cells);
|
||||
|
||||
/*
|
||||
* Create an mbus address windows.
|
||||
* FIXME: Remove this, together with the above code, once the
|
||||
* address windows are declared in the device tree.
|
||||
*/
|
||||
err = mvebu_mbus_add_window(devbus_wins[cs], base, size);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* We need to create a child device explicitly from here to
|
||||
* guarantee that the child will be probed after the timing
|
||||
* parameters for the bus are written.
|
||||
*/
|
||||
err = of_platform_populate(node, NULL, NULL, dev);
|
||||
if (err < 0) {
|
||||
mvebu_mbus_del_window(base, size);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mvebu_devbus_of_match[] = {
|
||||
{ .compatible = "marvell,mvebu-devbus" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
|
||||
|
||||
static struct platform_driver mvebu_devbus_driver = {
|
||||
.probe = mvebu_devbus_probe,
|
||||
.driver = {
|
||||
.name = "mvebu-devbus",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mvebu_devbus_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mvebu_devbus_init(void)
|
||||
{
|
||||
return platform_driver_register(&mvebu_devbus_driver);
|
||||
}
|
||||
module_init(mvebu_devbus_init);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");
|
||||
Loading…
Reference in New Issue