drm/amdgpu: update GFX MGCG settings
Update GFX MGCG related settings. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -7777,11 +7777,11 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
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{
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uint32_t data, def;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG))
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if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
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return;
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/* It is disabled by HW by default */
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if (enable) {
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
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/* 0 - Disable some blocks' MGCG */
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WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
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WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
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@ -7794,6 +7794,7 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
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RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
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if (def != data)
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@ -7816,13 +7817,15 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
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WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
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}
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}
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} else {
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} else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
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/* 1 - MGCG_OVERRIDE */
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def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
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data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
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RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
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RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
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if (def != data)
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WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
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