- add MT8183 support to mutex driver
MMSYS: - use per SoC array to describe the possible routing - add support for MT8183 Power management domains: - fix the case of a domain fails to get added - add names for each power domain to make debugging easier PMIC wrapper: - add support for PMIC wrapper with integrated arbiter - add support for MT8192/MT6873 -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmBl0JgXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH7R2BAArIiOQfH2+Ua71gQtPSoss4SX 1+j7pqfTAzHsLILC7SldGR7uBjUz9KjvuHab6lrZ5SMn2A6vF8IPEpAH0vJUPrq/ PACXese3VVlpDb3JjxcMSbFcuRW/f7Jptt1Kjss7IpwVYXgPWy/prWQdNIvX8uTn 15wa7JwljXsMjqBJdUYvBOYHDqyTuvqXPjGkwKTxKKRK843qUZ1ZT0lr0yux0p4R 83xh0MdqPNMzV02vNISd9fVJ4uL3Vv/k4vQXv5LOE1wnTgWKq4QPGvRxz8XOqcu9 y6EodyxMi2igTnnMXrGJTowB3j9j0FMWWKCTj8b8UmESbrk8VxtZjV4YTUJFlwks EVke23hsiqQA4i4NWw+zduB9KCHRBqemt5Z20uGIEXj2I9dvUw94+ScTOkYsNE8h B+wsFLQgPbD4wrzfs+GkX30c2D0uV8PLDtiQFmszbGHCslvXhwmdhp9wyOkA748L JyZzQhkJUyq9rCDwQtsKfmdLKTfj0GDOEuzjInI22WgcZiU8n23/SKaS+dYQH6+E Piz1MAzQGZuqQ2Xnp+2GyBrIZutyjuID0i3KbjuamJ6DHCiwq0u8t/fqWwFNB4oe YlCE4Gh7IP0/8q0t1uPNyO4EC1Nr9tiq6ahUUG5w4RgzhdVwqBf9IcumohLHEKfH tz3S2E92w09h+z/TpKY= =o2Cq -----END PGP SIGNATURE----- Merge tag 'v5.12-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers - add MT8183 support to mutex driver MMSYS: - use per SoC array to describe the possible routing - add support for MT8183 Power management domains: - fix the case of a domain fails to get added - add names for each power domain to make debugging easier PMIC wrapper: - add support for PMIC wrapper with integrated arbiter - add support for MT8192/MT6873 * tag 'v5.12-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: pm-domains: Add a power domain names for mt8167 soc: mediatek: pm-domains: Add a power domain names for mt8192 soc: mediatek: pm-domains: Add a power domain names for mt8183 soc: mediatek: pm-domains: Add a meaningful power domain name soc: mediatek: Make symbol 'mtk_mutex_driver' static soc: mediatek: mmsys: Add mt8183 mmsys routing table soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs dt-bindings: mediatek: add compatible for MT6873/8192 pwrap soc: mediatek: pwrap: add arbiter capability soc: mediatek: pwrap: use BIT() macro soc: mediatek: pm-domains: Fix missing error code in scpsys_add_subdomain() soc: mediatek: mmsys: Use an array for setting the routing registers soc: mediatek: mmsys: Create struct mtk_mmsys to store context data soc: mediatek: add mtk mutex support for MT8183 Link: https://lore.kernel.org/r/c47d4bdd-9e05-c0de-bacb-3a262fed936d@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
3e7f2f2980
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@ -22,6 +22,7 @@ Required properties in pwrap device node.
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"mediatek,mt6765-pwrap" for MT6765 SoCs
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"mediatek,mt6779-pwrap" for MT6779 SoCs
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"mediatek,mt6797-pwrap" for MT6797 SoCs
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"mediatek,mt6873-pwrap" for MT6873/8192 SoCs
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"mediatek,mt7622-pwrap" for MT7622 SoCs
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"mediatek,mt8135-pwrap" for MT8135 SoCs
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"mediatek,mt8173-pwrap" for MT8173 SoCs
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@ -15,6 +15,7 @@
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static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
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[MT8167_POWER_DOMAIN_MM] = {
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.name = "mm",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = SPM_DIS_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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@ -26,6 +27,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8167_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.sram_pdn_bits = GENMASK(8, 8),
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@ -33,6 +35,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8167_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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@ -40,6 +43,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8167_POWER_DOMAIN_MFG_ASYNC] = {
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.name = "mfg_async",
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.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
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.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
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.sram_pdn_bits = 0,
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@ -50,18 +54,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
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},
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},
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[MT8167_POWER_DOMAIN_MFG_2D] = {
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.name = "mfg_2d",
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.sta_mask = MT8167_PWR_STATUS_MFG_2D,
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.ctl_offs = SPM_MFG_2D_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8167_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = SPM_MFG_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8167_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = SPM_CONN_PWR_CON,
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.sram_pdn_bits = GENMASK(8, 8),
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@ -12,24 +12,28 @@
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static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
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[MT8173_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8173_POWER_DOMAIN_VENC] = {
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.name = "venc",
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.sta_mask = PWR_STATUS_VENC,
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.ctl_offs = SPM_VEN_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8173_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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},
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[MT8173_POWER_DOMAIN_MM] = {
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.name = "mm",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = SPM_DIS_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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@ -40,18 +44,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
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},
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},
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[MT8173_POWER_DOMAIN_VENC_LT] = {
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.name = "venc_lt",
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.sta_mask = PWR_STATUS_VENC_LT,
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.ctl_offs = SPM_VEN2_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8173_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = PWR_STATUS_AUDIO,
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.ctl_offs = SPM_AUDIO_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8173_POWER_DOMAIN_USB] = {
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.name = "usb",
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.sta_mask = PWR_STATUS_USB,
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.ctl_offs = SPM_USB_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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@ -59,18 +66,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
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.name = "mfg_async",
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.sta_mask = PWR_STATUS_MFG_ASYNC,
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.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = 0,
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},
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[MT8173_POWER_DOMAIN_MFG_2D] = {
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.name = "mfg_2d",
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.sta_mask = PWR_STATUS_MFG_2D,
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.ctl_offs = SPM_MFG_2D_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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},
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[MT8173_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = SPM_MFG_PWR_CON,
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.sram_pdn_bits = GENMASK(13, 8),
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@ -0,0 +1,54 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8183_MMSYS_H
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#define __SOC_MEDIATEK_MT8183_MMSYS_H
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#define MT8183_DISP_OVL0_MOUT_EN 0xf00
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#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
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#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
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#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
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#define MT8183_DISP_PATH0_SEL_IN 0xf24
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#define MT8183_DISP_DSI0_SEL_IN 0xf2c
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#define MT8183_DISP_DPI0_SEL_IN 0xf30
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#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
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#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
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#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
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#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
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#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
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#define MT8183_DITHER0_MOUT_IN_DSI0 BIT(0)
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#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
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#define MT8183_DSI0_SEL_IN_RDMA0 0x1
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#define MT8183_DSI0_SEL_IN_RDMA1 0x3
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#define MT8183_DPI0_SEL_IN_RDMA0 0x1
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#define MT8183_DPI0_SEL_IN_RDMA1 0x2
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#define MT8183_RDMA0_SOUT_COLOR0 0x1
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#define MT8183_RDMA1_SOUT_DSI0 0x1
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static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
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MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
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}, {
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DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
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MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
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}
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};
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#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
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@ -12,12 +12,14 @@
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static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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[MT8183_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = PWR_STATUS_AUDIO,
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.ctl_offs = 0x0314,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8183_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = 0x032c,
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.sram_pdn_bits = 0,
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@ -28,12 +30,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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},
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},
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[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
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.name = "mfg_async",
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.sta_mask = PWR_STATUS_MFG_ASYNC,
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.ctl_offs = 0x0334,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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},
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[MT8183_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = 0x0338,
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.sram_pdn_bits = GENMASK(8, 8),
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@ -41,18 +45,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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.caps = MTK_SCPD_DOMAIN_SUPPLY,
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},
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[MT8183_POWER_DOMAIN_MFG_CORE0] = {
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.name = "mfg_core0",
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.sta_mask = BIT(7),
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.ctl_offs = 0x034c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8183_POWER_DOMAIN_MFG_CORE1] = {
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.name = "mfg_core1",
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.sta_mask = BIT(20),
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.ctl_offs = 0x0310,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8183_POWER_DOMAIN_MFG_2D] = {
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.name = "mfg_2d",
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.sta_mask = PWR_STATUS_MFG_2D,
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.ctl_offs = 0x0348,
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.sram_pdn_bits = GENMASK(8, 8),
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@ -65,6 +72,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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},
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},
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[MT8183_POWER_DOMAIN_DISP] = {
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.name = "disp",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = 0x030c,
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.sram_pdn_bits = GENMASK(8, 8),
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@ -83,6 +91,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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},
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},
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[MT8183_POWER_DOMAIN_CAM] = {
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.name = "cam",
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.sta_mask = BIT(25),
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.ctl_offs = 0x0344,
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.sram_pdn_bits = GENMASK(9, 8),
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@ -105,6 +114,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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},
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},
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[MT8183_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = 0x0308,
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.sram_pdn_bits = GENMASK(9, 8),
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@ -127,6 +137,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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},
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},
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[MT8183_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = BIT(31),
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.ctl_offs = 0x0300,
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||||
.sram_pdn_bits = GENMASK(8, 8),
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||||
|
|
@ -139,6 +150,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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|||
},
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||||
},
|
||||
[MT8183_POWER_DOMAIN_VENC] = {
|
||||
.name = "venc",
|
||||
.sta_mask = PWR_STATUS_VENC,
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||||
.ctl_offs = 0x0304,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
|
|
@ -151,6 +163,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
|
|||
},
|
||||
},
|
||||
[MT8183_POWER_DOMAIN_VPU_TOP] = {
|
||||
.name = "vpu_top",
|
||||
.sta_mask = BIT(26),
|
||||
.ctl_offs = 0x0324,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -177,6 +190,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
|
|||
},
|
||||
},
|
||||
[MT8183_POWER_DOMAIN_VPU_CORE0] = {
|
||||
.name = "vpu_core0",
|
||||
.sta_mask = BIT(27),
|
||||
.ctl_offs = 0x33c,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
|
|
@ -194,6 +208,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
|
|||
.caps = MTK_SCPD_SRAM_ISO,
|
||||
},
|
||||
[MT8183_POWER_DOMAIN_VPU_CORE1] = {
|
||||
.name = "vpu_core1",
|
||||
.sta_mask = BIT(28),
|
||||
.ctl_offs = 0x0340,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
||||
[MT8192_POWER_DOMAIN_AUDIO] = {
|
||||
.name = "audio",
|
||||
.sta_mask = BIT(21),
|
||||
.ctl_offs = 0x0354,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -24,6 +25,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_CONN] = {
|
||||
.name = "conn",
|
||||
.sta_mask = PWR_STATUS_CONN,
|
||||
.ctl_offs = 0x0304,
|
||||
.sram_pdn_bits = 0,
|
||||
|
|
@ -45,12 +47,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MFG0] = {
|
||||
.name = "mfg0",
|
||||
.sta_mask = BIT(2),
|
||||
.ctl_offs = 0x0308,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MFG1] = {
|
||||
.name = "mfg1",
|
||||
.sta_mask = BIT(3),
|
||||
.ctl_offs = 0x030c,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -75,36 +79,42 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MFG2] = {
|
||||
.name = "mfg2",
|
||||
.sta_mask = BIT(4),
|
||||
.ctl_offs = 0x0310,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MFG3] = {
|
||||
.name = "mfg3",
|
||||
.sta_mask = BIT(5),
|
||||
.ctl_offs = 0x0314,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MFG4] = {
|
||||
.name = "mfg4",
|
||||
.sta_mask = BIT(6),
|
||||
.ctl_offs = 0x0318,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MFG5] = {
|
||||
.name = "mfg5",
|
||||
.sta_mask = BIT(7),
|
||||
.ctl_offs = 0x031c,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MFG6] = {
|
||||
.name = "mfg6",
|
||||
.sta_mask = BIT(8),
|
||||
.ctl_offs = 0x0320,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_DISP] = {
|
||||
.name = "disp",
|
||||
.sta_mask = BIT(20),
|
||||
.ctl_offs = 0x0350,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -133,6 +143,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_IPE] = {
|
||||
.name = "ipe",
|
||||
.sta_mask = BIT(14),
|
||||
.ctl_offs = 0x0338,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -149,6 +160,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_ISP] = {
|
||||
.name = "isp",
|
||||
.sta_mask = BIT(12),
|
||||
.ctl_offs = 0x0330,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -165,6 +177,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_ISP2] = {
|
||||
.name = "isp2",
|
||||
.sta_mask = BIT(13),
|
||||
.ctl_offs = 0x0334,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -181,6 +194,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_MDP] = {
|
||||
.name = "mdp",
|
||||
.sta_mask = BIT(19),
|
||||
.ctl_offs = 0x034c,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -197,6 +211,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_VENC] = {
|
||||
.name = "venc",
|
||||
.sta_mask = BIT(17),
|
||||
.ctl_offs = 0x0344,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -213,6 +228,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_VDEC] = {
|
||||
.name = "vdec",
|
||||
.sta_mask = BIT(15),
|
||||
.ctl_offs = 0x033c,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -229,12 +245,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_VDEC2] = {
|
||||
.name = "vdec2",
|
||||
.sta_mask = BIT(16),
|
||||
.ctl_offs = 0x0340,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_CAM] = {
|
||||
.name = "cam",
|
||||
.sta_mask = BIT(23),
|
||||
.ctl_offs = 0x035c,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
@ -263,18 +281,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
|
|||
},
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_CAM_RAWA] = {
|
||||
.name = "cam_rawa",
|
||||
.sta_mask = BIT(24),
|
||||
.ctl_offs = 0x0360,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_CAM_RAWB] = {
|
||||
.name = "cam_rawb",
|
||||
.sta_mask = BIT(25),
|
||||
.ctl_offs = 0x0364,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(12, 12),
|
||||
},
|
||||
[MT8192_POWER_DOMAIN_CAM_RAWC] = {
|
||||
.name = "cam_rawc",
|
||||
.sta_mask = BIT(26),
|
||||
.ctl_offs = 0x0368,
|
||||
.sram_pdn_bits = GENMASK(8, 8),
|
||||
|
|
|
|||
|
|
@ -10,79 +10,19 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/soc/mediatek/mtk-mmsys.h>
|
||||
|
||||
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
|
||||
#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
|
||||
#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
|
||||
#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
|
||||
#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
|
||||
#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
|
||||
#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
|
||||
#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
|
||||
#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
|
||||
#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
|
||||
#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
|
||||
#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
|
||||
#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
|
||||
#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
|
||||
|
||||
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
|
||||
#define DISP_REG_CONFIG_OUT_SEL 0x04c
|
||||
#define DISP_REG_CONFIG_DSI_SEL 0x050
|
||||
#define DISP_REG_CONFIG_DPI_SEL 0x064
|
||||
|
||||
#define OVL0_MOUT_EN_COLOR0 0x1
|
||||
#define OD_MOUT_EN_RDMA0 0x1
|
||||
#define OD1_MOUT_EN_RDMA1 BIT(16)
|
||||
#define UFOE_MOUT_EN_DSI0 0x1
|
||||
#define COLOR0_SEL_IN_OVL0 0x1
|
||||
#define OVL1_MOUT_EN_COLOR1 0x1
|
||||
#define GAMMA_MOUT_EN_RDMA1 0x1
|
||||
#define RDMA0_SOUT_DPI0 0x2
|
||||
#define RDMA0_SOUT_DPI1 0x3
|
||||
#define RDMA0_SOUT_DSI1 0x1
|
||||
#define RDMA0_SOUT_DSI2 0x4
|
||||
#define RDMA0_SOUT_DSI3 0x5
|
||||
#define RDMA1_SOUT_DPI0 0x2
|
||||
#define RDMA1_SOUT_DPI1 0x3
|
||||
#define RDMA1_SOUT_DSI1 0x1
|
||||
#define RDMA1_SOUT_DSI2 0x4
|
||||
#define RDMA1_SOUT_DSI3 0x5
|
||||
#define RDMA2_SOUT_DPI0 0x2
|
||||
#define RDMA2_SOUT_DPI1 0x3
|
||||
#define RDMA2_SOUT_DSI1 0x1
|
||||
#define RDMA2_SOUT_DSI2 0x4
|
||||
#define RDMA2_SOUT_DSI3 0x5
|
||||
#define DPI0_SEL_IN_RDMA1 0x1
|
||||
#define DPI0_SEL_IN_RDMA2 0x3
|
||||
#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
|
||||
#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
|
||||
#define DSI0_SEL_IN_RDMA1 0x1
|
||||
#define DSI0_SEL_IN_RDMA2 0x4
|
||||
#define DSI1_SEL_IN_RDMA1 0x1
|
||||
#define DSI1_SEL_IN_RDMA2 0x4
|
||||
#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
|
||||
#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
|
||||
#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
|
||||
#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
|
||||
#define COLOR1_SEL_IN_OVL1 0x1
|
||||
|
||||
#define OVL_MOUT_EN_RDMA 0x1
|
||||
#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
|
||||
#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
|
||||
#define DSI_SEL_IN_BLS 0x0
|
||||
#define DPI_SEL_IN_BLS 0x0
|
||||
#define DSI_SEL_IN_RDMA 0x1
|
||||
|
||||
struct mtk_mmsys_driver_data {
|
||||
const char *clk_driver;
|
||||
};
|
||||
#include "mtk-mmsys.h"
|
||||
#include "mt8183-mmsys.h"
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt2701-mm",
|
||||
.routes = mmsys_default_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt2712-mm",
|
||||
.routes = mmsys_default_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
|
||||
|
|
@ -95,186 +35,35 @@ static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
|
|||
|
||||
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt8173-mm",
|
||||
.routes = mmsys_default_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt8183-mm",
|
||||
.routes = mmsys_mt8183_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
|
||||
};
|
||||
|
||||
static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next,
|
||||
unsigned int *addr)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
|
||||
value = OVL0_MOUT_EN_COLOR0;
|
||||
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
|
||||
value = OVL_MOUT_EN_RDMA;
|
||||
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
|
||||
value = OD_MOUT_EN_RDMA0;
|
||||
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
|
||||
value = UFOE_MOUT_EN_DSI0;
|
||||
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
|
||||
value = OVL1_MOUT_EN_COLOR1;
|
||||
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
|
||||
value = GAMMA_MOUT_EN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
|
||||
value = OD1_MOUT_EN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
|
||||
value = RDMA0_SOUT_DPI0;
|
||||
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
|
||||
value = RDMA0_SOUT_DPI1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
|
||||
value = RDMA0_SOUT_DSI1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
|
||||
value = RDMA0_SOUT_DSI2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
|
||||
value = RDMA0_SOUT_DSI3;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
|
||||
value = RDMA1_SOUT_DSI1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
|
||||
value = RDMA1_SOUT_DSI2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
|
||||
value = RDMA1_SOUT_DSI3;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
|
||||
value = RDMA1_SOUT_DPI0;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
|
||||
value = RDMA1_SOUT_DPI1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
|
||||
value = RDMA2_SOUT_DPI0;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
|
||||
value = RDMA2_SOUT_DPI1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
|
||||
value = RDMA2_SOUT_DSI1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
|
||||
value = RDMA2_SOUT_DSI2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
|
||||
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
|
||||
value = RDMA2_SOUT_DSI3;
|
||||
} else {
|
||||
value = 0;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next,
|
||||
unsigned int *addr)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
|
||||
*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
|
||||
value = COLOR0_SEL_IN_OVL0;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
|
||||
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
|
||||
value = DPI0_SEL_IN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
|
||||
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
|
||||
value = DPI1_SEL_IN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
|
||||
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
|
||||
value = DSI0_SEL_IN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
|
||||
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
|
||||
value = DSI1_SEL_IN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
|
||||
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
|
||||
value = DSI2_SEL_IN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
|
||||
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
|
||||
value = DSI3_SEL_IN_RDMA1;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
|
||||
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
|
||||
value = DPI0_SEL_IN_RDMA2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
|
||||
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
|
||||
value = DPI1_SEL_IN_RDMA2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
|
||||
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
|
||||
value = DSI0_SEL_IN_RDMA2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
|
||||
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
|
||||
value = DSI1_SEL_IN_RDMA2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
|
||||
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
|
||||
value = DSI2_SEL_IN_RDMA2;
|
||||
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
|
||||
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
|
||||
value = DSI3_SEL_IN_RDMA2;
|
||||
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
|
||||
*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
|
||||
value = COLOR1_SEL_IN_OVL1;
|
||||
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
|
||||
*addr = DISP_REG_CONFIG_DSI_SEL;
|
||||
value = DSI_SEL_IN_BLS;
|
||||
} else {
|
||||
value = 0;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
|
||||
enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next)
|
||||
{
|
||||
if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
|
||||
writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
|
||||
config_regs + DISP_REG_CONFIG_OUT_SEL);
|
||||
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
|
||||
writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
|
||||
config_regs + DISP_REG_CONFIG_OUT_SEL);
|
||||
writel_relaxed(DSI_SEL_IN_RDMA,
|
||||
config_regs + DISP_REG_CONFIG_DSI_SEL);
|
||||
writel_relaxed(DPI_SEL_IN_BLS,
|
||||
config_regs + DISP_REG_CONFIG_DPI_SEL);
|
||||
}
|
||||
}
|
||||
struct mtk_mmsys {
|
||||
void __iomem *regs;
|
||||
const struct mtk_mmsys_driver_data *data;
|
||||
};
|
||||
|
||||
void mtk_mmsys_ddp_connect(struct device *dev,
|
||||
enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next)
|
||||
{
|
||||
void __iomem *config_regs = dev_get_drvdata(dev);
|
||||
unsigned int addr, value, reg;
|
||||
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
|
||||
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
|
||||
u32 reg;
|
||||
int i;
|
||||
|
||||
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
|
||||
if (value) {
|
||||
reg = readl_relaxed(config_regs + addr) | value;
|
||||
writel_relaxed(reg, config_regs + addr);
|
||||
}
|
||||
|
||||
mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
|
||||
|
||||
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
|
||||
if (value) {
|
||||
reg = readl_relaxed(config_regs + addr) | value;
|
||||
writel_relaxed(reg, config_regs + addr);
|
||||
}
|
||||
for (i = 0; i < mmsys->data->num_routes; i++)
|
||||
if (cur == routes[i].from_comp && next == routes[i].to_comp) {
|
||||
reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val;
|
||||
writel_relaxed(reg, mmsys->regs + routes[i].addr);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
|
||||
|
||||
|
|
@ -282,44 +71,42 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
|
|||
enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next)
|
||||
{
|
||||
void __iomem *config_regs = dev_get_drvdata(dev);
|
||||
unsigned int addr, value, reg;
|
||||
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
|
||||
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
|
||||
u32 reg;
|
||||
int i;
|
||||
|
||||
value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
|
||||
if (value) {
|
||||
reg = readl_relaxed(config_regs + addr) & ~value;
|
||||
writel_relaxed(reg, config_regs + addr);
|
||||
}
|
||||
|
||||
value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
|
||||
if (value) {
|
||||
reg = readl_relaxed(config_regs + addr) & ~value;
|
||||
writel_relaxed(reg, config_regs + addr);
|
||||
}
|
||||
for (i = 0; i < mmsys->data->num_routes; i++)
|
||||
if (cur == routes[i].from_comp && next == routes[i].to_comp) {
|
||||
reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val;
|
||||
writel_relaxed(reg, mmsys->regs + routes[i].addr);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
|
||||
|
||||
static int mtk_mmsys_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct mtk_mmsys_driver_data *data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct platform_device *clks;
|
||||
struct platform_device *drm;
|
||||
void __iomem *config_regs;
|
||||
struct mtk_mmsys *mmsys;
|
||||
int ret;
|
||||
|
||||
config_regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(config_regs)) {
|
||||
ret = PTR_ERR(config_regs);
|
||||
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
|
||||
if (!mmsys)
|
||||
return -ENOMEM;
|
||||
|
||||
mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(mmsys->regs)) {
|
||||
ret = PTR_ERR(mmsys->regs);
|
||||
dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, config_regs);
|
||||
mmsys->data = of_device_get_match_data(&pdev->dev);
|
||||
platform_set_drvdata(pdev, mmsys);
|
||||
|
||||
data = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
clks = platform_device_register_data(&pdev->dev, data->clk_driver,
|
||||
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
|
||||
PLATFORM_DEVID_AUTO, NULL, 0);
|
||||
if (IS_ERR(clks))
|
||||
return PTR_ERR(clks);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,215 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __SOC_MEDIATEK_MTK_MMSYS_H
|
||||
#define __SOC_MEDIATEK_MTK_MMSYS_H
|
||||
|
||||
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
|
||||
#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
|
||||
#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
|
||||
#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
|
||||
#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
|
||||
#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
|
||||
#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
|
||||
#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
|
||||
#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
|
||||
#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
|
||||
#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
|
||||
#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
|
||||
#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
|
||||
#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
|
||||
|
||||
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
|
||||
#define DISP_REG_CONFIG_OUT_SEL 0x04c
|
||||
#define DISP_REG_CONFIG_DSI_SEL 0x050
|
||||
#define DISP_REG_CONFIG_DPI_SEL 0x064
|
||||
|
||||
#define OVL0_MOUT_EN_COLOR0 0x1
|
||||
#define OD_MOUT_EN_RDMA0 0x1
|
||||
#define OD1_MOUT_EN_RDMA1 BIT(16)
|
||||
#define UFOE_MOUT_EN_DSI0 0x1
|
||||
#define COLOR0_SEL_IN_OVL0 0x1
|
||||
#define OVL1_MOUT_EN_COLOR1 0x1
|
||||
#define GAMMA_MOUT_EN_RDMA1 0x1
|
||||
#define RDMA0_SOUT_DPI0 0x2
|
||||
#define RDMA0_SOUT_DPI1 0x3
|
||||
#define RDMA0_SOUT_DSI1 0x1
|
||||
#define RDMA0_SOUT_DSI2 0x4
|
||||
#define RDMA0_SOUT_DSI3 0x5
|
||||
#define RDMA1_SOUT_DPI0 0x2
|
||||
#define RDMA1_SOUT_DPI1 0x3
|
||||
#define RDMA1_SOUT_DSI1 0x1
|
||||
#define RDMA1_SOUT_DSI2 0x4
|
||||
#define RDMA1_SOUT_DSI3 0x5
|
||||
#define RDMA2_SOUT_DPI0 0x2
|
||||
#define RDMA2_SOUT_DPI1 0x3
|
||||
#define RDMA2_SOUT_DSI1 0x1
|
||||
#define RDMA2_SOUT_DSI2 0x4
|
||||
#define RDMA2_SOUT_DSI3 0x5
|
||||
#define DPI0_SEL_IN_RDMA1 0x1
|
||||
#define DPI0_SEL_IN_RDMA2 0x3
|
||||
#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
|
||||
#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
|
||||
#define DSI0_SEL_IN_RDMA1 0x1
|
||||
#define DSI0_SEL_IN_RDMA2 0x4
|
||||
#define DSI1_SEL_IN_RDMA1 0x1
|
||||
#define DSI1_SEL_IN_RDMA2 0x4
|
||||
#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
|
||||
#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
|
||||
#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
|
||||
#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
|
||||
#define COLOR1_SEL_IN_OVL1 0x1
|
||||
|
||||
#define OVL_MOUT_EN_RDMA 0x1
|
||||
#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
|
||||
#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
|
||||
#define DSI_SEL_IN_BLS 0x0
|
||||
#define DPI_SEL_IN_BLS 0x0
|
||||
#define DSI_SEL_IN_RDMA 0x1
|
||||
|
||||
struct mtk_mmsys_routes {
|
||||
u32 from_comp;
|
||||
u32 to_comp;
|
||||
u32 addr;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
struct mtk_mmsys_driver_data {
|
||||
const char *clk_driver;
|
||||
const struct mtk_mmsys_routes *routes;
|
||||
const unsigned int num_routes;
|
||||
};
|
||||
|
||||
/*
|
||||
* Routes in mt8173, mt2701, mt2712 are different. That means
|
||||
* in the same register address, it controls different input/output
|
||||
* selection for each SoC. But, right now, they use the same table as
|
||||
* default routes meet their requirements. But we don't have the complete
|
||||
* route information for these three SoC, so just keep them in the same
|
||||
* table. After we've more information, we could separate mt2701, mt2712
|
||||
* to an independent table.
|
||||
*/
|
||||
static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
|
||||
{
|
||||
DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
|
||||
DISP_REG_CONFIG_OUT_SEL, BLS_TO_DSI_RDMA1_TO_DPI1
|
||||
}, {
|
||||
DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
|
||||
DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_BLS
|
||||
}, {
|
||||
DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI
|
||||
}, {
|
||||
DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_RDMA
|
||||
}, {
|
||||
DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_BLS
|
||||
}, {
|
||||
DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
|
||||
DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
|
||||
DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0
|
||||
}, {
|
||||
DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
|
||||
DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
|
||||
DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
|
||||
DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
|
||||
DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
|
||||
DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
|
||||
DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI0
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
|
||||
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
|
||||
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
|
||||
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
|
||||
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI3
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI0
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
|
||||
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
|
||||
DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
|
||||
DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
|
||||
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
|
||||
DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
|
||||
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
|
||||
DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
|
||||
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI3
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
|
||||
DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI0
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
|
||||
DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
|
||||
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
|
||||
DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
|
||||
DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
|
||||
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
|
||||
DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
|
||||
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
|
||||
DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA2
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
|
||||
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI3
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
|
||||
DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA2
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
|
||||
|
|
@ -14,6 +14,8 @@
|
|||
|
||||
#define MT2701_MUTEX0_MOD0 0x2c
|
||||
#define MT2701_MUTEX0_SOF0 0x30
|
||||
#define MT8183_MUTEX0_MOD0 0x30
|
||||
#define MT8183_MUTEX0_SOF0 0x2c
|
||||
|
||||
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
|
||||
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
|
||||
|
|
@ -37,6 +39,18 @@
|
|||
#define MT8167_MUTEX_MOD_DISP_DITHER 15
|
||||
#define MT8167_MUTEX_MOD_DISP_UFOE 16
|
||||
|
||||
#define MT8183_MUTEX_MOD_DISP_RDMA0 0
|
||||
#define MT8183_MUTEX_MOD_DISP_RDMA1 1
|
||||
#define MT8183_MUTEX_MOD_DISP_OVL0 9
|
||||
#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
|
||||
#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
|
||||
#define MT8183_MUTEX_MOD_DISP_WDMA0 12
|
||||
#define MT8183_MUTEX_MOD_DISP_COLOR0 13
|
||||
#define MT8183_MUTEX_MOD_DISP_CCORR0 14
|
||||
#define MT8183_MUTEX_MOD_DISP_AAL0 15
|
||||
#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
|
||||
#define MT8183_MUTEX_MOD_DISP_DITHER0 17
|
||||
|
||||
#define MT8173_MUTEX_MOD_DISP_OVL0 11
|
||||
#define MT8173_MUTEX_MOD_DISP_OVL1 12
|
||||
#define MT8173_MUTEX_MOD_DISP_RDMA0 13
|
||||
|
|
@ -87,6 +101,11 @@
|
|||
#define MT2712_MUTEX_SOF_DSI3 6
|
||||
#define MT8167_MUTEX_SOF_DPI0 2
|
||||
#define MT8167_MUTEX_SOF_DPI1 3
|
||||
#define MT8183_MUTEX_SOF_DSI0 1
|
||||
#define MT8183_MUTEX_SOF_DPI0 2
|
||||
|
||||
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
|
||||
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
|
||||
|
||||
struct mtk_mutex {
|
||||
int id;
|
||||
|
|
@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
|||
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
|
||||
};
|
||||
|
||||
static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
||||
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
|
||||
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
|
||||
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
|
||||
[DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
|
||||
[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
|
||||
[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
|
||||
[DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
|
||||
[DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
|
||||
[DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
|
||||
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
|
||||
};
|
||||
|
||||
static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
||||
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
|
||||
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
|
||||
|
|
@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
|||
[MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
|
||||
};
|
||||
|
||||
/* Add EOF setting so overlay hardware can receive frame done irq */
|
||||
static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
||||
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
|
||||
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
|
||||
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
|
||||
};
|
||||
|
||||
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
|
||||
.mutex_mod = mt2701_mutex_mod,
|
||||
.mutex_sof = mt2712_mutex_sof,
|
||||
|
|
@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = {
|
|||
.mutex_sof_reg = MT2701_MUTEX0_SOF0,
|
||||
};
|
||||
|
||||
static const struct mtk_mutex_data mt8183_mutex_driver_data = {
|
||||
.mutex_mod = mt8183_mutex_mod,
|
||||
.mutex_sof = mt8183_mutex_sof,
|
||||
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
|
||||
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
|
||||
.no_clk = true,
|
||||
};
|
||||
|
||||
struct mtk_mutex *mtk_mutex_get(struct device *dev)
|
||||
{
|
||||
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
|
||||
|
|
@ -457,11 +505,13 @@ static const struct of_device_id mutex_driver_dt_match[] = {
|
|||
.data = &mt8167_mutex_driver_data},
|
||||
{ .compatible = "mediatek,mt8173-disp-mutex",
|
||||
.data = &mt8173_mutex_driver_data},
|
||||
{ .compatible = "mediatek,mt8183-disp-mutex",
|
||||
.data = &mt8183_mutex_driver_data},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
|
||||
|
||||
struct platform_driver mtk_mutex_driver = {
|
||||
static struct platform_driver mtk_mutex_driver = {
|
||||
.probe = mtk_mutex_probe,
|
||||
.remove = mtk_mutex_remove,
|
||||
.driver = {
|
||||
|
|
|
|||
|
|
@ -438,7 +438,11 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
|
|||
goto err_unprepare_subsys_clocks;
|
||||
}
|
||||
|
||||
pd->genpd.name = node->name;
|
||||
if (!pd->data->name)
|
||||
pd->genpd.name = node->name;
|
||||
else
|
||||
pd->genpd.name = pd->data->name;
|
||||
|
||||
pd->genpd.power_off = scpsys_power_off;
|
||||
pd->genpd.power_on = scpsys_power_on;
|
||||
|
||||
|
|
@ -487,8 +491,9 @@ static int scpsys_add_subdomain(struct scpsys *scpsys, struct device_node *paren
|
|||
|
||||
child_pd = scpsys_add_one_domain(scpsys, child);
|
||||
if (IS_ERR(child_pd)) {
|
||||
dev_err_probe(scpsys->dev, PTR_ERR(child_pd),
|
||||
"%pOF: failed to get child domain id\n", child);
|
||||
ret = PTR_ERR(child_pd);
|
||||
dev_err_probe(scpsys->dev, ret, "%pOF: failed to get child domain id\n",
|
||||
child);
|
||||
goto err_put_node;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ struct scpsys_bus_prot_data {
|
|||
|
||||
/**
|
||||
* struct scpsys_domain_data - scp domain data for power on/off flow
|
||||
* @name: The name of the power domain.
|
||||
* @sta_mask: The mask for power on/off status bit.
|
||||
* @ctl_offs: The offset for main power control register.
|
||||
* @sram_pdn_bits: The mask for sram power control bits.
|
||||
|
|
@ -85,6 +86,7 @@ struct scpsys_bus_prot_data {
|
|||
* @bp_smi: bus protection for smi subsystem
|
||||
*/
|
||||
struct scpsys_domain_data {
|
||||
const char *name;
|
||||
u32 sta_mask;
|
||||
int ctl_offs;
|
||||
u32 sram_pdn_bits;
|
||||
|
|
|
|||
|
|
@ -25,10 +25,12 @@
|
|||
|
||||
/* macro for wrapper status */
|
||||
#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
|
||||
#define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007)
|
||||
#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
|
||||
#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
|
||||
#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
|
||||
#define PWRAP_STATE_INIT_DONE0 (1 << 21)
|
||||
#define PWRAP_STATE_SYNC_IDLE0 BIT(20)
|
||||
#define PWRAP_STATE_INIT_DONE0 BIT(21)
|
||||
#define PWRAP_STATE_INIT_DONE1 BIT(15)
|
||||
|
||||
/* macro for WACS FSM */
|
||||
#define PWRAP_WACS_FSM_IDLE 0x00
|
||||
|
|
@ -74,6 +76,7 @@
|
|||
#define PWRAP_CAP_DCM BIT(2)
|
||||
#define PWRAP_CAP_INT1_EN BIT(3)
|
||||
#define PWRAP_CAP_WDT_SRC1 BIT(4)
|
||||
#define PWRAP_CAP_ARB BIT(5)
|
||||
|
||||
/* defines for slave device wrapper registers */
|
||||
enum dew_regs {
|
||||
|
|
@ -340,6 +343,8 @@ enum pwrap_regs {
|
|||
PWRAP_DCM_DBC_PRD,
|
||||
PWRAP_EINT_STA0_ADR,
|
||||
PWRAP_EINT_STA1_ADR,
|
||||
PWRAP_SWINF_2_WDATA_31_0,
|
||||
PWRAP_SWINF_2_RDATA_31_0,
|
||||
|
||||
/* MT2701 only regs */
|
||||
PWRAP_ADC_CMD_ADDR,
|
||||
|
|
@ -627,6 +632,17 @@ static int mt6797_regs[] = {
|
|||
[PWRAP_DCM_DBC_PRD] = 0x1D4,
|
||||
};
|
||||
|
||||
static int mt6873_regs[] = {
|
||||
[PWRAP_INIT_DONE2] = 0x0,
|
||||
[PWRAP_TIMER_EN] = 0x3E0,
|
||||
[PWRAP_INT_EN] = 0x448,
|
||||
[PWRAP_WACS2_CMD] = 0xC80,
|
||||
[PWRAP_SWINF_2_WDATA_31_0] = 0xC84,
|
||||
[PWRAP_SWINF_2_RDATA_31_0] = 0xC94,
|
||||
[PWRAP_WACS2_VLDCLR] = 0xCA4,
|
||||
[PWRAP_WACS2_RDATA] = 0xCA8,
|
||||
};
|
||||
|
||||
static int mt7622_regs[] = {
|
||||
[PWRAP_MUX_SEL] = 0x0,
|
||||
[PWRAP_WRAP_EN] = 0x4,
|
||||
|
|
@ -1045,6 +1061,7 @@ enum pwrap_type {
|
|||
PWRAP_MT6765,
|
||||
PWRAP_MT6779,
|
||||
PWRAP_MT6797,
|
||||
PWRAP_MT6873,
|
||||
PWRAP_MT7622,
|
||||
PWRAP_MT8135,
|
||||
PWRAP_MT8173,
|
||||
|
|
@ -1106,18 +1123,25 @@ static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
|
|||
writel(val, wrp->base + wrp->master->regs[reg]);
|
||||
}
|
||||
|
||||
static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
|
||||
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
|
||||
return PWRAP_GET_WACS_ARB_FSM(val);
|
||||
else
|
||||
return PWRAP_GET_WACS_FSM(val);
|
||||
}
|
||||
|
||||
static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
|
||||
{
|
||||
u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
|
||||
|
||||
return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
|
||||
return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE;
|
||||
}
|
||||
|
||||
static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
|
||||
{
|
||||
u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
|
||||
|
||||
return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
|
||||
return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1165,6 +1189,7 @@ static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
|
|||
static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
|
||||
if (ret) {
|
||||
|
|
@ -1172,13 +1197,21 @@ static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
|
|||
return ret;
|
||||
}
|
||||
|
||||
pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
|
||||
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
|
||||
val = adr;
|
||||
else
|
||||
val = (adr >> 1) << 16;
|
||||
pwrap_writel(wrp, val, PWRAP_WACS2_CMD);
|
||||
|
||||
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
*rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
|
||||
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
|
||||
val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);
|
||||
else
|
||||
val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
|
||||
*rdata = PWRAP_GET_WACS_RDATA(val);
|
||||
|
||||
pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
|
||||
|
||||
|
|
@ -1228,8 +1261,13 @@ static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
|
|||
return ret;
|
||||
}
|
||||
|
||||
pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
|
||||
PWRAP_WACS2_CMD);
|
||||
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
|
||||
pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
|
||||
pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
|
||||
} else {
|
||||
pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
|
||||
PWRAP_WACS2_CMD);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1485,6 +1523,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
|
|||
case PWRAP_MT7622:
|
||||
pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
|
||||
break;
|
||||
case PWRAP_MT6873:
|
||||
case PWRAP_MT8183:
|
||||
break;
|
||||
}
|
||||
|
|
@ -1921,6 +1960,19 @@ static const struct pmic_wrapper_type pwrap_mt6797 = {
|
|||
.init_soc_specific = NULL,
|
||||
};
|
||||
|
||||
static const struct pmic_wrapper_type pwrap_mt6873 = {
|
||||
.regs = mt6873_regs,
|
||||
.type = PWRAP_MT6873,
|
||||
.arb_en_all = 0x777f,
|
||||
.int_en_all = BIT(4) | BIT(5),
|
||||
.int1_en_all = 0,
|
||||
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
|
||||
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
|
||||
.caps = PWRAP_CAP_ARB,
|
||||
.init_reg_clock = pwrap_common_init_reg_clock,
|
||||
.init_soc_specific = NULL,
|
||||
};
|
||||
|
||||
static const struct pmic_wrapper_type pwrap_mt7622 = {
|
||||
.regs = mt7622_regs,
|
||||
.type = PWRAP_MT7622,
|
||||
|
|
@ -1998,6 +2050,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
|
|||
}, {
|
||||
.compatible = "mediatek,mt6797-pwrap",
|
||||
.data = &pwrap_mt6797,
|
||||
}, {
|
||||
.compatible = "mediatek,mt6873-pwrap",
|
||||
.data = &pwrap_mt6873,
|
||||
}, {
|
||||
.compatible = "mediatek,mt7622-pwrap",
|
||||
.data = &pwrap_mt7622,
|
||||
|
|
@ -2022,6 +2077,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
|
|||
static int pwrap_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret, irq;
|
||||
u32 mask_done;
|
||||
struct pmic_wrapper *wrp;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *of_slave_id = NULL;
|
||||
|
|
@ -2116,14 +2172,21 @@ static int pwrap_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
|
||||
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
|
||||
mask_done = PWRAP_STATE_INIT_DONE1;
|
||||
else
|
||||
mask_done = PWRAP_STATE_INIT_DONE0;
|
||||
|
||||
if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) {
|
||||
dev_dbg(wrp->dev, "initialization isn't finished\n");
|
||||
ret = -ENODEV;
|
||||
goto err_out2;
|
||||
}
|
||||
|
||||
/* Initialize watchdog, may not be done by the bootloader */
|
||||
pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
|
||||
if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
|
||||
pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
|
||||
|
||||
/*
|
||||
* Since STAUPD was not used on mt8173 platform,
|
||||
* so STAUPD of WDT_SRC which should be turned off
|
||||
|
|
@ -2132,7 +2195,11 @@ static int pwrap_probe(struct platform_device *pdev)
|
|||
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
|
||||
pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
|
||||
|
||||
pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
|
||||
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
|
||||
pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
|
||||
else
|
||||
pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
|
||||
|
||||
pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
|
||||
/*
|
||||
* We add INT1 interrupt to handle starvation and request exception
|
||||
|
|
|
|||
Loading…
Reference in New Issue