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riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node 

Add PLL clocks input from PLL clocks driver in SYSCRG node.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu 2023-07-17 10:30:40 +08:00 committed by Conor Dooley
parent 3fcbcfc496
commit 3e6670a28b
1 changed files with 6 additions and 2 deletions
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8
arch/riscv/boot/dts/starfive/jh7110.dtsi
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@ -517,12 +517,16 @@
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>;
<&tdm_ext>, <&mclk_ext>,
<&pllclk JH7110_PLLCLK_PLL0_OUT>,
<&pllclk JH7110_PLLCLK_PLL1_OUT>,
<&pllclk JH7110_PLLCLK_PLL2_OUT>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
"tdm_ext", "mclk_ext";
"tdm_ext", "mclk_ext",
"pll0_out", "pll1_out", "pll2_out";
#clock-cells = <1>;
#reset-cells = <1>;
};