drm/amdgpu: add I2C_CLASS_HWMON to SMU i2c buses
Not sure that this really matters that much, but these could have various other hwmon chips on them. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
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@ -665,7 +665,7 @@ int smu_v11_0_i2c_control_init(struct i2c_adapter *control)
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mutex_init(&adev->pm.smu_i2c_mutex);
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control->owner = THIS_MODULE;
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control->class = I2C_CLASS_SPD;
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control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
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control->dev.parent = &adev->pdev->dev;
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control->algo = &smu_v11_0_i2c_algo;
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snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
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@ -2033,7 +2033,7 @@ static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter
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int res;
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control->owner = THIS_MODULE;
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control->class = I2C_CLASS_SPD;
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control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
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control->dev.parent = &adev->pdev->dev;
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control->algo = &arcturus_i2c_algo;
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snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
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@ -2832,7 +2832,7 @@ static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *
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int res;
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control->owner = THIS_MODULE;
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control->class = I2C_CLASS_SPD;
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control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
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control->dev.parent = &adev->pdev->dev;
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control->algo = &navi10_i2c_algo;
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snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
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@ -3539,7 +3539,7 @@ static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_a
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int res;
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control->owner = THIS_MODULE;
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control->class = I2C_CLASS_SPD;
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control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
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control->dev.parent = &adev->pdev->dev;
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control->algo = &sienna_cichlid_i2c_algo;
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snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
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