media: ccs-pll: Split off VT subtree calculation
Split off the VT sub clock tree calculation from the rest, into its own function. Also call the op_pll_fr argument pll_fr, since soon these may not be OP tree values. This paves way for additional features in the future such as dual PLL support. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Sakari Ailus
Mauro Carvalho Chehab
parent
8030aa4f9c
commit
3e2db036c9
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@ -149,6 +149,146 @@ static int check_all_bounds(struct device *dev,
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#define DPHY_CONST 16
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#define PHY_CONST_DIV 16
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static void
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__ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
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const struct ccs_pll_branch_limits_bk *op_lim_bk,
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struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
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struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
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uint32_t phy_const)
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{
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uint32_t sys_div;
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uint32_t best_pix_div = INT_MAX >> 1;
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uint32_t vt_op_binning_div;
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uint32_t min_vt_div, max_vt_div, vt_div;
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uint32_t min_sys_div, max_sys_div;
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/*
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* Some sensors perform analogue binning and some do this
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* digitally. The ones doing this digitally can be roughly be
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* found out using this formula. The ones doing this digitally
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* should run at higher clock rate, so smaller divisor is used
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* on video timing side.
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*/
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if (lim->min_line_length_pck_bin > lim->min_line_length_pck
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/ pll->binning_horizontal)
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vt_op_binning_div = pll->binning_horizontal;
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else
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vt_op_binning_div = 1;
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dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
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/*
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* Profile 2 supports vt_pix_clk_div E [4, 10]
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*
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* Horizontal binning can be used as a base for difference in
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* divisors. One must make sure that horizontal blanking is
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* enough to accommodate the CSI-2 sync codes.
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*
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* Take scaling factor and number of VT lanes into account as well.
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*
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* Find absolute limits for the factor of vt divider.
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*/
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dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
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min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div
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* pll->scale_n * pll->vt_lanes * phy_const,
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(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
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pll->csi2.lanes : 1)
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* vt_op_binning_div * pll->scale_m
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* PHY_CONST_DIV);
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/* Find smallest and biggest allowed vt divisor. */
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dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
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min_vt_div = max(min_vt_div,
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DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
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lim->vt_bk.max_pix_clk_freq_hz));
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dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
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min_vt_div);
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min_vt_div = max_t(uint32_t, min_vt_div,
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lim->vt_bk.min_pix_clk_div
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* lim->vt_bk.min_sys_clk_div);
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dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
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max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
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dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
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max_vt_div = min(max_vt_div,
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DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
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lim->vt_bk.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
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max_vt_div);
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/*
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* Find limitsits for sys_clk_div. Not all values are possible
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* with all values of pix_clk_div.
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*/
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min_sys_div = lim->vt_bk.min_sys_clk_div;
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dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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DIV_ROUND_UP(min_vt_div,
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lim->vt_bk.max_pix_clk_div));
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dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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pll_fr->pll_op_clk_freq_hz
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/ lim->vt_bk.max_sys_clk_freq_hz);
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dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
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min_sys_div = clk_div_even_up(min_sys_div);
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dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
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max_sys_div = lim->vt_bk.max_sys_clk_div;
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dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(max_vt_div,
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lim->vt_bk.min_pix_clk_div));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
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lim->vt_bk.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
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/*
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* Find pix_div such that a legal pix_div * sys_div results
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* into a value which is not smaller than div, the desired
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* divisor.
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*/
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for (vt_div = min_vt_div; vt_div <= max_vt_div;
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vt_div += 2 - (vt_div & 1)) {
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for (sys_div = min_sys_div;
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sys_div <= max_sys_div;
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sys_div += 2 - (sys_div & 1)) {
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uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
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uint16_t rounded_div;
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if (pix_div < lim->vt_bk.min_pix_clk_div
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|| pix_div > lim->vt_bk.max_pix_clk_div) {
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dev_dbg(dev,
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"pix_div %u too small or too big (%u--%u)\n",
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pix_div,
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lim->vt_bk.min_pix_clk_div,
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lim->vt_bk.max_pix_clk_div);
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continue;
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}
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rounded_div = roundup(vt_div, best_pix_div);
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/* Check if this one is better. */
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if (pix_div * sys_div <= rounded_div)
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best_pix_div = pix_div;
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/* Bail out if we've already found the best value. */
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if (vt_div == rounded_div)
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break;
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}
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if (best_pix_div < INT_MAX >> 1)
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break;
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}
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pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
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pll->vt_bk.pix_clk_div = best_pix_div;
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pll->vt_bk.sys_clk_freq_hz =
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pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
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pll->vt_bk.pix_clk_freq_hz =
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pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
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}
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/*
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* Heuristically guess the PLL tree for a given common multiplier and
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* divisor. Begin with the operational timing and continue to video
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@ -168,9 +308,6 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
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struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
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uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
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{
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uint32_t sys_div;
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uint32_t best_pix_div = INT_MAX >> 1;
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uint32_t vt_op_binning_div;
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/*
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* Higher multipliers (and divisors) are often required than
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* necessitated by the external clock and the output clocks.
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@ -179,8 +316,6 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
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*/
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uint32_t more_mul_min, more_mul_max;
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uint32_t more_mul_factor;
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uint32_t min_vt_div, max_vt_div, vt_div;
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uint32_t min_sys_div, max_sys_div;
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uint32_t i;
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/*
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@ -269,138 +404,10 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
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dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
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if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
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/* No OP clocks --- VT clocks are used instead. */
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goto out_skip_vt_calc;
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}
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if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS))
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__ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
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op_pll_bk, cphy, phy_const);
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/*
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* Some sensors perform analogue binning and some do this
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* digitally. The ones doing this digitally can be roughly be
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* found out using this formula. The ones doing this digitally
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* should run at higher clock rate, so smaller divisor is used
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* on video timing side.
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*/
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if (lim->min_line_length_pck_bin > lim->min_line_length_pck
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/ pll->binning_horizontal)
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vt_op_binning_div = pll->binning_horizontal;
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else
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vt_op_binning_div = 1;
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dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
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/*
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* Profile 2 supports vt_pix_clk_div E [4, 10]
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*
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* Horizontal binning can be used as a base for difference in
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* divisors. One must make sure that horizontal blanking is
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* enough to accommodate the CSI-2 sync codes.
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*
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* Take scaling factor and number of VT lanes into account as well.
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*
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* Find absolute limits for the factor of vt divider.
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*/
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dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
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min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div
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* pll->scale_n * pll->vt_lanes * phy_const,
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(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
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pll->csi2.lanes : 1)
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* vt_op_binning_div * pll->scale_m
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* PHY_CONST_DIV);
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/* Find smallest and biggest allowed vt divisor. */
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dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
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min_vt_div = max(min_vt_div,
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DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
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lim->vt_bk.max_pix_clk_freq_hz));
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dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
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min_vt_div);
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min_vt_div = max_t(uint32_t, min_vt_div,
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lim->vt_bk.min_pix_clk_div
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* lim->vt_bk.min_sys_clk_div);
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dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
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max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
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dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
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max_vt_div = min(max_vt_div,
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DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
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lim->vt_bk.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
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max_vt_div);
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/*
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* Find limitsits for sys_clk_div. Not all values are possible
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* with all values of pix_clk_div.
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*/
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min_sys_div = lim->vt_bk.min_sys_clk_div;
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dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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DIV_ROUND_UP(min_vt_div,
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lim->vt_bk.max_pix_clk_div));
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dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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op_pll_fr->pll_op_clk_freq_hz
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/ lim->vt_bk.max_sys_clk_freq_hz);
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dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
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min_sys_div = clk_div_even_up(min_sys_div);
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dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
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max_sys_div = lim->vt_bk.max_sys_clk_div;
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dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(max_vt_div,
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lim->vt_bk.min_pix_clk_div));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
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lim->vt_bk.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
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/*
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* Find pix_div such that a legal pix_div * sys_div results
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* into a value which is not smaller than div, the desired
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* divisor.
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*/
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for (vt_div = min_vt_div; vt_div <= max_vt_div;
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vt_div += 2 - (vt_div & 1)) {
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for (sys_div = min_sys_div;
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sys_div <= max_sys_div;
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sys_div += 2 - (sys_div & 1)) {
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uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
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uint16_t rounded_div;
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if (pix_div < lim->vt_bk.min_pix_clk_div
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|| pix_div > lim->vt_bk.max_pix_clk_div) {
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dev_dbg(dev,
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"pix_div %u too small or too big (%u--%u)\n",
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pix_div,
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lim->vt_bk.min_pix_clk_div,
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lim->vt_bk.max_pix_clk_div);
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continue;
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}
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rounded_div = roundup(vt_div, best_pix_div);
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/* Check if this one is better. */
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if (pix_div * sys_div <= rounded_div)
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best_pix_div = pix_div;
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/* Bail out if we've already found the best value. */
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if (vt_div == rounded_div)
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break;
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}
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if (best_pix_div < INT_MAX >> 1)
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break;
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}
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pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
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pll->vt_bk.pix_clk_div = best_pix_div;
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pll->vt_bk.sys_clk_freq_hz =
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op_pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
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pll->vt_bk.pix_clk_freq_hz =
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pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
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out_skip_vt_calc:
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pll->pixel_rate_pixel_array =
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pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
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