e1000 endianness annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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3e18826c73
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@ -595,35 +595,35 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
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/* Receive Descriptor */
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struct e1000_rx_desc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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uint16_t length; /* Length of data DMAed into data buffer */
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uint16_t csum; /* Packet checksum */
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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__le16 length; /* Length of data DMAed into data buffer */
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__le16 csum; /* Packet checksum */
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uint8_t status; /* Descriptor status */
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uint8_t errors; /* Descriptor Errors */
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uint16_t special;
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__le16 special;
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};
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/* Receive Descriptor - Extended */
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union e1000_rx_desc_extended {
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struct {
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uint64_t buffer_addr;
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uint64_t reserved;
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__le64 buffer_addr;
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__le64 reserved;
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} read;
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struct {
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struct {
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uint32_t mrq; /* Multiple Rx Queues */
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__le32 mrq; /* Multiple Rx Queues */
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union {
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uint32_t rss; /* RSS Hash */
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__le32 rss; /* RSS Hash */
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struct {
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uint16_t ip_id; /* IP id */
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uint16_t csum; /* Packet Checksum */
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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uint32_t status_error; /* ext status/error */
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uint16_t length;
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uint16_t vlan; /* VLAN tag */
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__le32 status_error; /* ext status/error */
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__le16 length;
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__le16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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@ -633,29 +633,29 @@ union e1000_rx_desc_extended {
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union e1000_rx_desc_packet_split {
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struct {
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/* one buffer for protocol header(s), three data buffers */
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uint64_t buffer_addr[MAX_PS_BUFFERS];
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__le64 buffer_addr[MAX_PS_BUFFERS];
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} read;
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struct {
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struct {
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uint32_t mrq; /* Multiple Rx Queues */
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__le32 mrq; /* Multiple Rx Queues */
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union {
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uint32_t rss; /* RSS Hash */
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__le32 rss; /* RSS Hash */
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struct {
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uint16_t ip_id; /* IP id */
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uint16_t csum; /* Packet Checksum */
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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uint32_t status_error; /* ext status/error */
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uint16_t length0; /* length of buffer 0 */
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uint16_t vlan; /* VLAN tag */
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__le32 status_error; /* ext status/error */
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__le16 length0; /* length of buffer 0 */
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__le16 vlan; /* VLAN tag */
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} middle;
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struct {
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uint16_t header_status;
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uint16_t length[3]; /* length of buffers 1-3 */
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__le16 header_status;
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__le16 length[3]; /* length of buffers 1-3 */
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} upper;
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uint64_t reserved;
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__le64 reserved;
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} wb; /* writeback */
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};
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@ -715,21 +715,21 @@ union e1000_rx_desc_packet_split {
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/* Transmit Descriptor */
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struct e1000_tx_desc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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union {
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uint32_t data;
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__le32 data;
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struct {
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uint16_t length; /* Data buffer length */
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__le16 length; /* Data buffer length */
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uint8_t cso; /* Checksum offset */
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uint8_t cmd; /* Descriptor control */
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} flags;
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} lower;
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union {
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uint32_t data;
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__le32 data;
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struct {
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uint8_t status; /* Descriptor status */
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uint8_t css; /* Checksum start */
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uint16_t special;
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__le16 special;
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} fields;
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} upper;
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};
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@ -759,49 +759,49 @@ struct e1000_tx_desc {
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/* Offload Context Descriptor */
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struct e1000_context_desc {
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union {
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uint32_t ip_config;
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__le32 ip_config;
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struct {
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uint8_t ipcss; /* IP checksum start */
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uint8_t ipcso; /* IP checksum offset */
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uint16_t ipcse; /* IP checksum end */
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__le16 ipcse; /* IP checksum end */
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} ip_fields;
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} lower_setup;
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union {
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uint32_t tcp_config;
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__le32 tcp_config;
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struct {
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uint8_t tucss; /* TCP checksum start */
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uint8_t tucso; /* TCP checksum offset */
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uint16_t tucse; /* TCP checksum end */
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__le16 tucse; /* TCP checksum end */
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} tcp_fields;
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} upper_setup;
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uint32_t cmd_and_length; /* */
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__le32 cmd_and_length; /* */
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union {
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uint32_t data;
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__le32 data;
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struct {
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uint8_t status; /* Descriptor status */
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uint8_t hdr_len; /* Header length */
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uint16_t mss; /* Maximum segment size */
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__le16 mss; /* Maximum segment size */
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} fields;
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} tcp_seg_setup;
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};
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/* Offload data descriptor */
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struct e1000_data_desc {
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uint64_t buffer_addr; /* Address of the descriptor's buffer address */
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__le64 buffer_addr; /* Address of the descriptor's buffer address */
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union {
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uint32_t data;
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__le32 data;
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struct {
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uint16_t length; /* Data buffer length */
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__le16 length; /* Data buffer length */
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uint8_t typ_len_ext; /* */
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uint8_t cmd; /* */
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} flags;
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} lower;
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union {
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uint32_t data;
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__le32 data;
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struct {
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uint8_t status; /* Descriptor status */
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uint8_t popts; /* Packet Options */
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uint16_t special; /* */
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__le16 special; /* */
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} fields;
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} upper;
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};
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@ -817,8 +817,8 @@ struct e1000_data_desc {
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/* Receive Address Register */
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struct e1000_rar {
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volatile uint32_t low; /* receive address low */
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volatile uint32_t high; /* receive address high */
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volatile __le32 low; /* receive address low */
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volatile __le32 high; /* receive address high */
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};
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/* Number of entries in the Multicast Table Array (MTA). */
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@ -272,14 +272,14 @@ module_exit(e1000_exit_module);
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static int e1000_request_irq(struct e1000_adapter *adapter)
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{
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struct net_device *netdev = adapter->netdev;
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void (*handler) = &e1000_intr;
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irq_handler_t handler = e1000_intr;
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int irq_flags = IRQF_SHARED;
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int err;
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if (adapter->hw.mac_type >= e1000_82571) {
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adapter->have_msi = !pci_enable_msi(adapter->pdev);
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if (adapter->have_msi) {
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handler = &e1000_intr_msi;
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handler = e1000_intr_msi;
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irq_flags = 0;
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}
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}
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@ -4092,8 +4092,8 @@ e1000_rx_checksum(struct e1000_adapter *adapter,
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/* Hardware complements the payload checksum, so we undo it
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* and then put the value in host order for further stack use.
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*/
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csum = ntohl(csum ^ 0xFFFF);
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skb->csum = csum;
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__sum16 sum = (__force __sum16)htons(csum);
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skb->csum = csum_unfold(~sum);
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skb->ip_summed = CHECKSUM_COMPLETE;
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}
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adapter->hw_csum_good++;
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@ -4621,7 +4621,7 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
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rx_desc->read.buffer_addr[j+1] =
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cpu_to_le64(ps_page_dma->ps_page_dma[j]);
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} else
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rx_desc->read.buffer_addr[j+1] = ~0;
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rx_desc->read.buffer_addr[j+1] = ~cpu_to_le64(0);
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}
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skb = netdev_alloc_skb(netdev,
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