bnx2x: Add a periodic task for link PHY events
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@conan.davemloft.net>
This commit is contained in:
Yaniv Rosner
David S. Miller
parent
0d40f0d425
commit
3deb8167ea
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@ -1160,6 +1160,8 @@ struct bnx2x {
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struct delayed_work sp_task;
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struct delayed_work reset_task;
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struct delayed_work period_task;
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struct timer_list timer;
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int current_interval;
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@ -1940,4 +1942,5 @@ static const u32 dmae_reg_go_c[] = {
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};
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void bnx2x_set_ethtool_ops(struct net_device *netdev);
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void bnx2x_notify_link_changed(struct bnx2x *bp);
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#endif /* bnx2x.h */
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@ -1736,9 +1736,16 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
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(load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
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(load_code == FW_MSG_CODE_DRV_LOAD_PORT))
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(load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
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bp->port.pmf = 1;
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else
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/*
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* We need the barrier to ensure the ordering between the
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* writing to bp->port.pmf here and reading it from the
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* bnx2x_periodic_task().
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*/
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smp_mb();
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queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
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} else
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bp->port.pmf = 0;
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DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
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@ -296,6 +296,23 @@ static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
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/******************************************************************/
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/* EPIO/GPIO section */
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/******************************************************************/
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static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
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{
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u32 epio_mask, gp_oenable;
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*en = 0;
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/* Sanity check */
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if (epio_pin > 31) {
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DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
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return;
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}
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epio_mask = 1 << epio_pin;
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/* Set this EPIO to output */
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gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
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REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
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*en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
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}
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static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
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{
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u32 epio_mask, gp_output, gp_oenable;
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@ -334,6 +351,20 @@ static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
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}
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}
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static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
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{
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if (pin_cfg == PIN_CFG_NA)
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return -EINVAL;
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if (pin_cfg >= PIN_CFG_EPIO0) {
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bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
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} else {
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u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
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u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
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*val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
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}
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return 0;
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}
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/******************************************************************/
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/* ETS section */
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/******************************************************************/
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@ -2537,6 +2568,12 @@ static int bnx2x_bmac1_enable(struct link_params *params,
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REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
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wb_data, 2);
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if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
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REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS,
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wb_data, 2);
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if (wb_data[0] > 0)
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return -ESRCH;
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}
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return 0;
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}
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@ -2602,6 +2639,16 @@ static int bnx2x_bmac2_enable(struct link_params *params,
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udelay(30);
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bnx2x_update_pfc_bmac2(params, vars, is_lb);
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if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
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REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT,
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wb_data, 2);
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if (wb_data[0] > 0) {
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DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n",
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wb_data[0]);
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return -ESRCH;
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}
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}
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return 0;
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}
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@ -6081,7 +6128,7 @@ static int bnx2x_update_link_down(struct link_params *params,
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DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
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bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
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vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
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/* indicate no mac active */
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vars->mac_type = MAC_TYPE_NONE;
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@ -6126,6 +6173,7 @@ static int bnx2x_update_link_up(struct link_params *params,
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int rc = 0;
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vars->link_status |= LINK_STATUS_LINK_UP;
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vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
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if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
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vars->link_status |=
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@ -6135,9 +6183,15 @@ static int bnx2x_update_link_up(struct link_params *params,
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vars->link_status |=
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LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
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if (USES_WARPCORE(bp)) {
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if (link_10g)
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bnx2x_xmac_enable(params, vars, 0);
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else
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if (link_10g) {
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if (bnx2x_xmac_enable(params, vars, 0) ==
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-ESRCH) {
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DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
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vars->link_up = 0;
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vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
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vars->link_status &= ~LINK_STATUS_LINK_UP;
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}
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} else
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bnx2x_umac_enable(params, vars, 0);
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bnx2x_set_led(params, vars,
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LED_MODE_OPER, vars->line_speed);
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@ -6145,7 +6199,13 @@ static int bnx2x_update_link_up(struct link_params *params,
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if ((CHIP_IS_E1x(bp) ||
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CHIP_IS_E2(bp))) {
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if (link_10g) {
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bnx2x_bmac_enable(params, vars, 0);
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if (bnx2x_bmac_enable(params, vars, 0) ==
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-ESRCH) {
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DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
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vars->link_up = 0;
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vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
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vars->link_status &= ~LINK_STATUS_LINK_UP;
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}
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bnx2x_set_led(params, vars,
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LED_MODE_OPER, SPEED_10000);
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@ -6199,7 +6259,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
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u8 is_mi_int = 0;
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u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
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u8 active_external_phy = INT_PHY;
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vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
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for (phy_index = INT_PHY; phy_index < params->num_phys;
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phy_index++) {
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phy_vars[phy_index].flow_ctrl = 0;
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@ -8109,6 +8169,10 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
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u32 tx_en_mode;
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u16 cnt, val, tmp1;
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struct bnx2x *bp = params->bp;
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/* SPF+ PHY: Set flag to check for Tx error */
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vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
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MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
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/* HW reset */
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@ -8292,6 +8356,9 @@ static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
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struct bnx2x *bp = params->bp;
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DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
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/* SPF+ PHY: Set flag to check for Tx error */
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vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
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bnx2x_wait_reset_complete(bp, phy, params);
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@ -8460,6 +8527,9 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
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struct bnx2x *bp = params->bp;
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/* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
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/* SPF+ PHY: Set flag to check for Tx error */
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vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
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bnx2x_wait_reset_complete(bp, phy, params);
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rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
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/* Should be 0x6 to enable XS on Tx side. */
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@ -11832,6 +11902,135 @@ int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
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return rc;
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}
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static void bnx2x_check_over_curr(struct link_params *params,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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u32 cfg_pin;
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u8 port = params->port;
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u32 pin_val;
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cfg_pin = (REG_RD(bp, params->shmem_base +
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offsetof(struct shmem_region,
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dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
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PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
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PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
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/* Ignore check if no external input PIN available */
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if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
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return;
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if (!pin_val) {
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if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
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netdev_err(bp->dev, "Error: Power fault on Port %d has"
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" been detected and the power to "
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"that SFP+ module has been removed"
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" to prevent failure of the card."
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" Please remove the SFP+ module and"
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" restart the system to clear this"
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" error.\n",
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params->port);
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vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
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}
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} else
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vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
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}
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static void bnx2x_analyze_link_error(struct link_params *params,
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struct link_vars *vars, u32 lss_status)
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{
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struct bnx2x *bp = params->bp;
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/* Compare new value with previous value */
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u8 led_mode;
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u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
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/*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n",
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vars->link_up,
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half_open_conn, lss_status);*/
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if ((lss_status ^ half_open_conn) == 0)
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return;
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/* If values differ */
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DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
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half_open_conn, lss_status);
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/*
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* a. Update shmem->link_status accordingly
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* b. Update link_vars->link_up
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*/
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if (lss_status) {
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vars->link_status &= ~LINK_STATUS_LINK_UP;
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vars->link_up = 0;
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vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
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/*
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* Set LED mode to off since the PHY doesn't know about these
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* errors
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*/
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led_mode = LED_MODE_OFF;
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} else {
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vars->link_status |= LINK_STATUS_LINK_UP;
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vars->link_up = 1;
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vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
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led_mode = LED_MODE_OPER;
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}
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/* Update the LED according to the link state */
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bnx2x_set_led(params, vars, led_mode, SPEED_10000);
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/* Update link status in the shared memory */
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bnx2x_update_mng(params, vars->link_status);
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/* C. Trigger General Attention */
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vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
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bnx2x_notify_link_changed(bp);
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}
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static void bnx2x_check_half_open_conn(struct link_params *params,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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u32 lss_status = 0;
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u32 mac_base;
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/* In case link status is physically up @ 10G do */
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if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
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return;
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if (!CHIP_IS_E3(bp) &&
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(REG_RD(bp, MISC_REG_RESET_REG_2) &
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(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) {
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/* Check E1X / E2 BMAC */
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u32 lss_status_reg;
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u32 wb_data[2];
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mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
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NIG_REG_INGRESS_BMAC0_MEM;
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/* Read BIGMAC_REGISTER_RX_LSS_STATUS */
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if (CHIP_IS_E2(bp))
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lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
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else
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lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
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REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
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lss_status = (wb_data[0] > 0);
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bnx2x_analyze_link_error(params, vars, lss_status);
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}
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}
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void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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if (!params) {
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DP(NETIF_MSG_LINK, "Ininitliazed params !\n");
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return;
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}
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/* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x
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RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed,
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REG_RD(bp, MISC_REG_RESET_REG_2)); */
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bnx2x_check_half_open_conn(params, vars);
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if (CHIP_IS_E3(bp))
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bnx2x_check_over_curr(params, vars);
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}
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u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
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{
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u8 phy_index;
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@ -271,6 +271,10 @@ struct link_vars {
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u8 phy_flags;
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#define PHY_XGXS_FLAG (1<<0)
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#define PHY_SGMII_FLAG (1<<1)
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#define PHY_PHYSICAL_LINK_FLAG (1<<2)
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#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
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#define PHY_OVER_CURRENT_FLAG (1<<4)
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#define PHY_TX_ERROR_CHECK_FLAG (1<<5)
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u8 mac_type;
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#define MAC_TYPE_NONE 0
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@ -292,7 +296,9 @@ struct link_vars {
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u32 link_status;
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u8 fault_detected;
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u8 rsrv1;
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u16 rsrv2;
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u16 periodic_flags;
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#define PERIODIC_FLAGS_LINK_EVENT 0x0001
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u32 aeu_int_mask;
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};
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@ -478,4 +484,7 @@ void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
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int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
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struct link_params *params);
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void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
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#endif /* BNX2X_LINK_H */
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@ -1563,6 +1563,7 @@ void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
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/* make sure sp_task is not running */
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cancel_delayed_work(&bp->sp_task);
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cancel_delayed_work(&bp->period_task);
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flush_workqueue(bnx2x_wq);
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}
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@ -2150,7 +2151,8 @@ u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
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if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
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bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
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bnx2x_link_report(bp);
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}
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} else
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queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
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bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
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return rc;
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}
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@ -2524,6 +2526,15 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
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bp->port.pmf = 1;
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DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
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/*
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* We need the mb() to ensure the ordering between the writing to
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* bp->port.pmf here and reading it from the bnx2x_periodic_task().
|
||||
*/
|
||||
smp_mb();
|
||||
|
||||
/* queue a periodic task */
|
||||
queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
|
||||
|
||||
bnx2x_dcbx_pmf_update(bp);
|
||||
|
||||
/* enable nig attention */
|
||||
|
|
@ -3242,8 +3253,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
|
|||
bnx2x_fan_failure(bp);
|
||||
}
|
||||
|
||||
if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
|
||||
AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
|
||||
if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
|
||||
bnx2x_acquire_phy_lock(bp);
|
||||
bnx2x_handle_module_detect_int(&bp->link_params);
|
||||
bnx2x_release_phy_lock(bp);
|
||||
|
|
@ -3360,17 +3370,27 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
|
|||
if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
|
||||
bnx2x_pmf_update(bp);
|
||||
|
||||
/* Always call it here: bnx2x_link_report() will
|
||||
* prevent the link indication duplication.
|
||||
*/
|
||||
bnx2x__link_status_update(bp);
|
||||
|
||||
if (bp->port.pmf &&
|
||||
(val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
|
||||
bp->dcbx_enabled > 0)
|
||||
/* start dcbx state machine */
|
||||
bnx2x_dcbx_set_params(bp,
|
||||
BNX2X_DCBX_STATE_NEG_RECEIVED);
|
||||
if (bp->link_vars.periodic_flags &
|
||||
PERIODIC_FLAGS_LINK_EVENT) {
|
||||
/* sync with link */
|
||||
bnx2x_acquire_phy_lock(bp);
|
||||
bp->link_vars.periodic_flags &=
|
||||
~PERIODIC_FLAGS_LINK_EVENT;
|
||||
bnx2x_release_phy_lock(bp);
|
||||
if (IS_MF(bp))
|
||||
bnx2x_link_sync_notify(bp);
|
||||
bnx2x_link_report(bp);
|
||||
}
|
||||
/* Always call it here: bnx2x_link_report() will
|
||||
* prevent the link indication duplication.
|
||||
*/
|
||||
bnx2x__link_status_update(bp);
|
||||
} else if (attn & BNX2X_MC_ASSERT_BITS) {
|
||||
|
||||
BNX2X_ERR("MC assert!\n");
|
||||
|
|
@ -8044,6 +8064,37 @@ reset_task_exit:
|
|||
|
||||
/* end of nic load/unload */
|
||||
|
||||
static void bnx2x_period_task(struct work_struct *work)
|
||||
{
|
||||
struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
|
||||
|
||||
if (!netif_running(bp->dev))
|
||||
goto period_task_exit;
|
||||
|
||||
if (CHIP_REV_IS_SLOW(bp)) {
|
||||
BNX2X_ERR("period task called on emulation, ignoring\n");
|
||||
goto period_task_exit;
|
||||
}
|
||||
|
||||
bnx2x_acquire_phy_lock(bp);
|
||||
/*
|
||||
* The barrier is needed to ensure the ordering between the writing to
|
||||
* the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
|
||||
* the reading here.
|
||||
*/
|
||||
smp_mb();
|
||||
if (bp->port.pmf) {
|
||||
bnx2x_period_func(&bp->link_params, &bp->link_vars);
|
||||
|
||||
/* Re-queue task in 1 sec */
|
||||
queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
|
||||
}
|
||||
|
||||
bnx2x_release_phy_lock(bp);
|
||||
period_task_exit:
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Init service functions
|
||||
*/
|
||||
|
|
@ -9237,7 +9288,7 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
|
|||
|
||||
INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
|
||||
INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
|
||||
|
||||
INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
|
||||
rc = bnx2x_get_hwinfo(bp);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
|
@ -10515,6 +10566,11 @@ static void __exit bnx2x_cleanup(void)
|
|||
destroy_workqueue(bnx2x_wq);
|
||||
}
|
||||
|
||||
void bnx2x_notify_link_changed(struct bnx2x *bp)
|
||||
{
|
||||
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
|
||||
}
|
||||
|
||||
module_init(bnx2x_init);
|
||||
module_exit(bnx2x_cleanup);
|
||||
|
||||
|
|
|
|||
|
|
@ -5559,6 +5559,7 @@
|
|||
#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
|
||||
#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
|
||||
#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
|
||||
#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
|
||||
#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
|
||||
#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
|
||||
#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
|
||||
|
|
@ -5574,6 +5575,7 @@
|
|||
#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
|
||||
#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
|
||||
#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
|
||||
#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
|
||||
#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
|
||||
#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
|
||||
#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
|
||||
|
|
|
|||
Loading…
Reference in New Issue