drm/amd/powerplay: Replace per-asic print_performance with generic
Replace per-asic print_current_performance() functions with generic that calls read_sensor. Tested on Tonga and Carrizo for aesthetics and accuracy. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom St Denis
Alex Deucher
parent
884031f0aa
commit
3de4ec5727
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@ -2343,6 +2343,11 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
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#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
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#define amdgpu_dpm_read_sensor(adev, idx, value) \
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((adev)->pp_enabled ? \
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(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
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-EINVAL)
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#define amdgpu_dpm_get_temperature(adev) \
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((adev)->pp_enabled ? \
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(adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
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@ -2394,11 +2399,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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(adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
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(adev)->pm.funcs->powergate_vce((adev), (g)))
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#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
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((adev)->pp_enabled ? \
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(adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
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(adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
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#define amdgpu_dpm_get_current_power_state(adev) \
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(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
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@ -1322,6 +1322,64 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
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{
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int32_t value;
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/* sanity check PP is enabled */
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if (!(adev->powerplay.pp_funcs &&
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adev->powerplay.pp_funcs->read_sensor))
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return -EINVAL;
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/* GPU Clocks */
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seq_printf(m, "GFX Clocks and Power:\n");
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, &value))
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seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, &value))
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seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, &value))
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seq_printf(m, "\t%u mV (VDDGFX)\n", value);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, &value))
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seq_printf(m, "\t%u mV (VDDNB)\n", value);
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seq_printf(m, "\n");
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/* GPU Temp */
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, &value))
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seq_printf(m, "GPU Temperature: %u C\n", value/1000);
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/* GPU Load */
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value))
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seq_printf(m, "GPU Load: %u %%\n", value);
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seq_printf(m, "\n");
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/* UVD clocks */
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, &value)) {
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if (!value) {
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seq_printf(m, "UVD: Disabled\n");
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} else {
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seq_printf(m, "UVD: Enabled\n");
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, &value))
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seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, &value))
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seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
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}
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}
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seq_printf(m, "\n");
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/* VCE clocks */
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, &value)) {
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if (!value) {
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seq_printf(m, "VCE: Disabled\n");
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} else {
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seq_printf(m, "VCE: Enabled\n");
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, &value))
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seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
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}
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}
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return 0;
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}
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static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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@ -1337,11 +1395,11 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
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(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
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seq_printf(m, "PX asic powered off\n");
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} else if (adev->pp_enabled) {
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amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
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return amdgpu_debugfs_pm_info_pp(m, adev);
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} else {
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mutex_lock(&adev->pm.mutex);
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if (adev->pm.funcs->debugfs_print_current_performance_level)
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amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
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adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
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else
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seq_printf(m, "Debugfs support not implemented for this asic\n");
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mutex_unlock(&adev->pm.mutex);
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@ -576,28 +576,6 @@ enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
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}
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}
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static void
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pp_debugfs_print_current_performance_level(void *handle,
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struct seq_file *m)
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{
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struct pp_hwmgr *hwmgr;
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if (handle == NULL)
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return;
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hwmgr = ((struct pp_instance *)handle)->hwmgr;
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if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
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return;
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if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
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printk(KERN_INFO "%s was not implemented.\n", __func__);
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return;
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}
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hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
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}
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static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
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{
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struct pp_hwmgr *hwmgr;
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@ -925,7 +903,6 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
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.powergate_vce = pp_dpm_powergate_vce,
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.powergate_uvd = pp_dpm_powergate_uvd,
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.dispatch_tasks = pp_dpm_dispatch_tasks,
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.print_current_performance_level = pp_debugfs_print_current_performance_level,
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.set_fan_control_mode = pp_dpm_set_fan_control_mode,
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.get_fan_control_mode = pp_dpm_get_fan_control_mode,
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.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
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@ -1538,78 +1538,6 @@ int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
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return sizeof(struct cz_power_state);
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}
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static void
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cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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struct phm_clock_voltage_dependency_table *table =
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hwmgr->dyn_state.vddc_dependency_on_sclk;
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struct phm_vce_clock_voltage_dependency_table *vce_table =
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hwmgr->dyn_state.vce_clock_voltage_dependency_table;
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struct phm_uvd_clock_voltage_dependency_table *uvd_table =
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hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
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uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
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TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
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uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
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TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
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uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
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TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
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uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
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uint16_t vddnb, vddgfx;
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int result;
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if (sclk_index >= NUM_SCLK_LEVELS) {
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seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
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} else {
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sclk = table->entries[sclk_index].clk;
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seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
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}
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tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
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CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
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vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
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tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
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CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
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vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
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seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
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seq_printf(m, "\n uvd %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
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if (!cz_hwmgr->uvd_power_gated) {
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if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
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seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
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} else {
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vclk = uvd_table->entries[uvd_index].vclk;
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dclk = uvd_table->entries[uvd_index].dclk;
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seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
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}
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}
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seq_printf(m, "\n vce %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
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if (!cz_hwmgr->vce_power_gated) {
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if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
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seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
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} else {
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ecclk = vce_table->entries[vce_index].ecclk;
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seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
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}
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}
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result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
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if (0 == result) {
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activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
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activity_percent = activity_percent > 100 ? 100 : activity_percent;
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} else {
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activity_percent = 50;
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}
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seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
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}
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static void cz_hw_print_display_cfg(
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const struct cc6_settings *cc6_settings)
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{
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@ -1947,6 +1875,12 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
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}
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*value = activity_percent;
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return 0;
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case AMDGPU_PP_SENSOR_UVD_POWER:
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*value = cz_hwmgr->uvd_power_gated ? 0 : 1;
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return 0;
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case AMDGPU_PP_SENSOR_VCE_POWER:
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*value = cz_hwmgr->vce_power_gated ? 0 : 1;
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return 0;
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default:
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return -EINVAL;
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}
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@ -1967,7 +1901,6 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
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.patch_boot_state = cz_dpm_patch_boot_state,
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.get_pp_table_entry = cz_dpm_get_pp_table_entry,
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.get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
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.print_current_perforce_level = cz_print_current_perforce_level,
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.set_cpu_power_state = cz_set_cpu_power_state,
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.store_cc6_data = cz_store_cc6_data,
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.force_clock_level = cz_force_clock_level,
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@ -3112,38 +3112,6 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
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return 0;
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}
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static void
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smu7_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
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{
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uint32_t sclk, mclk, activity_percent;
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uint32_t offset;
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
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sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
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smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
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mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
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seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
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mclk / 100, sclk / 100);
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offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
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SMU_SoftRegisters,
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AverageGraphicsActivity);
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activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
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activity_percent += 0x80;
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activity_percent >>= 8;
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seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
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seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
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seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
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}
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static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
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{
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uint32_t sclk, mclk, activity_percent;
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@ -3174,6 +3142,12 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
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case AMDGPU_PP_SENSOR_GPU_TEMP:
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*value = smu7_thermal_get_temperature(hwmgr);
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return 0;
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case AMDGPU_PP_SENSOR_UVD_POWER:
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*value = data->uvd_power_gated ? 0 : 1;
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return 0;
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case AMDGPU_PP_SENSOR_VCE_POWER:
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*value = data->vce_power_gated ? 0 : 1;
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return 0;
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default:
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return -EINVAL;
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}
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@ -4318,7 +4292,6 @@ static struct pp_hwmgr_func smu7_hwmgr_funcs = {
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.patch_boot_state = smu7_dpm_patch_boot_state,
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.get_pp_table_entry = smu7_get_pp_table_entry,
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.get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
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.print_current_perforce_level = smu7_print_current_perforce_level,
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.powerdown_uvd = smu7_powerdown_uvd,
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.powergate_uvd = smu7_powergate_uvd,
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.powergate_vce = smu7_powergate_vce,
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@ -39,6 +39,8 @@ enum amd_pp_sensors {
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AMDGPU_PP_SENSOR_GPU_LOAD,
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AMDGPU_PP_SENSOR_GFX_MCLK,
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AMDGPU_PP_SENSOR_GPU_TEMP,
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AMDGPU_PP_SENSOR_VCE_POWER,
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AMDGPU_PP_SENSOR_UVD_POWER,
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};
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enum amd_pp_event {
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@ -343,8 +345,6 @@ struct amd_powerplay_funcs {
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int (*powergate_uvd)(void *handle, bool gate);
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int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
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void *input, void *output);
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void (*print_current_performance_level)(void *handle,
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struct seq_file *m);
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int (*set_fan_control_mode)(void *handle, uint32_t mode);
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int (*get_fan_control_mode)(void *handle);
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int (*set_fan_speed_percent)(void *handle, uint32_t percent);
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@ -311,8 +311,6 @@ struct pp_hwmgr_func {
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int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
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int (*power_state_set)(struct pp_hwmgr *hwmgr,
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const void *state);
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void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
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struct seq_file *m);
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int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
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int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
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int (*display_config_changed)(struct pp_hwmgr *hwmgr);
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