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PCI: Support BAR sizes up to 8TB 

Current kernel reports that BARs larger than 128GB, e.g., this 4TB BAR, are
disabled:

    pci 0000:01:00.0: disabling BAR 4: [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000)

Increase the maximum BAR size from 128GB to 8TB for future expansion.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20220118092117.10089-1-liudongdong3@huawei.com
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Dongdong Liu 2022-01-18 17:21:17 +08:00 committed by Bjorn Helgaas
parent e783362eb5
commit 3dc8a1f6f6
1 changed files with 1 additions and 1 deletions
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2
drivers/pci/setup-bus.c
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@ -994,7 +994,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
{
struct pci_dev *dev;
resource_size_t min_align, align, size, size0, size1;
resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */
int order, max_order;
struct resource *b_res = find_bus_resource_of_type(bus,
mask | IORESOURCE_PREFETCH, type);