arm: zynq: slcr: Use read-modify-write for register writes
zynq_slcr_cpu_start/stop() ignored the current register state when writing to a register. Fixing this by implementing proper read-modify-write. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
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*/
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*/
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void zynq_slcr_cpu_start(int cpu)
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void zynq_slcr_cpu_start(int cpu)
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{
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{
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/* enable CPUn */
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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writel(SLCR_A9_CPU_CLKSTOP << cpu,
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reg &= ~(SLCR_A9_CPU_RST << cpu);
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zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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/* enable CLK for CPUn */
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reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
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writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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}
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/**
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/**
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@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
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*/
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*/
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void zynq_slcr_cpu_stop(int cpu)
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void zynq_slcr_cpu_stop(int cpu)
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{
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{
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/* stop CLK and reset CPUn */
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
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reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
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zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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}
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/**
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/**
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