mvebu soc changes for v4.3 (part #2)
SoC part of the Dove PMU series -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlXE0fgACgkQCwYYjhRyO9XUKwCeIOTx172942DUMzGwO3feDGZn zCgAn2yxrZaFqUo/EfVqgieeTGBmY6gh =gfKo -----END PGP SIGNATURE----- Merge tag 'mvebu-soc-4.3-2' of git://git.infradead.org/linux-mvebu into next/drivers mvebu soc changes for v4.3 (part #2) SoC part of the Dove PMU series * tag 'mvebu-soc-4.3-2' of git://git.infradead.org/linux-mvebu: ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
3d3cacc0b8
|
|
@ -96,6 +96,7 @@ config MACH_DOVE
|
|||
select MACH_MVEBU_ANY
|
||||
select ORION_IRQCHIP
|
||||
select ORION_TIMER
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select PINCTRL_DOVE
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the
|
||||
|
|
|
|||
|
|
@ -65,18 +65,6 @@ static const struct of_device_id of_coherency_table[] = {
|
|||
int ll_enable_coherency(void);
|
||||
void ll_add_cpu_to_smp_group(void);
|
||||
|
||||
int set_cpu_coherent(void)
|
||||
{
|
||||
if (!coherency_base) {
|
||||
pr_warn("Can't make current CPU cache coherent.\n");
|
||||
pr_warn("Coherency fabric is not initialized\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
ll_add_cpu_to_smp_group();
|
||||
return ll_enable_coherency();
|
||||
}
|
||||
|
||||
static int mvebu_hwcc_notifier(struct notifier_block *nb,
|
||||
unsigned long event, void *__dev)
|
||||
{
|
||||
|
|
@ -206,6 +194,23 @@ static int coherency_type(void)
|
|||
return type;
|
||||
}
|
||||
|
||||
int set_cpu_coherent(void)
|
||||
{
|
||||
int type = coherency_type();
|
||||
|
||||
if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
|
||||
if (!coherency_base) {
|
||||
pr_warn("Can't make current CPU cache coherent.\n");
|
||||
pr_warn("Coherency fabric is not initialized\n");
|
||||
return 1;
|
||||
}
|
||||
ll_add_cpu_to_smp_group();
|
||||
return ll_enable_coherency();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int coherency_available(void)
|
||||
{
|
||||
return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
|
||||
|
|
|
|||
|
|
@ -25,6 +25,6 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev);
|
|||
|
||||
void __iomem *mvebu_get_scu_base(void);
|
||||
|
||||
int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd));
|
||||
|
||||
int mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,
|
||||
u32 srcmd));
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/mbus.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/soc/dove/pmu.h>
|
||||
#include <asm/hardware/cache-tauros2.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include "common.h"
|
||||
|
|
@ -24,6 +25,7 @@ static void __init dove_init(void)
|
|||
tauros2_init(0);
|
||||
#endif
|
||||
BUG_ON(mvebu_mbus_dt_init(false));
|
||||
dove_init_pmu();
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Board-level suspend/resume support.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
* Copyright (C) 2014-2015 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
|
|
@ -20,27 +20,27 @@
|
|||
#include <linux/slab.h>
|
||||
#include "common.h"
|
||||
|
||||
#define ARMADA_XP_GP_PIC_NR_GPIOS 3
|
||||
#define ARMADA_PIC_NR_GPIOS 3
|
||||
|
||||
static void __iomem *gpio_ctrl;
|
||||
static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
|
||||
static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
|
||||
static int pic_gpios[ARMADA_PIC_NR_GPIOS];
|
||||
static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
|
||||
|
||||
static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
|
||||
static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
|
||||
{
|
||||
u32 reg, ackcmd;
|
||||
int i;
|
||||
|
||||
/* Put 001 as value on the GPIOs */
|
||||
reg = readl(gpio_ctrl);
|
||||
for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
|
||||
for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
|
||||
reg &= ~BIT(pic_raw_gpios[i]);
|
||||
reg |= BIT(pic_raw_gpios[0]);
|
||||
writel(reg, gpio_ctrl);
|
||||
|
||||
/* Prepare writing 111 to the GPIOs */
|
||||
ackcmd = readl(gpio_ctrl);
|
||||
for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
|
||||
for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
|
||||
ackcmd |= BIT(pic_raw_gpios[i]);
|
||||
|
||||
srcmd = cpu_to_le32(srcmd);
|
||||
|
|
@ -76,7 +76,7 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
|
|||
[ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
|
||||
}
|
||||
|
||||
static int mvebu_armada_xp_gp_pm_init(void)
|
||||
static int __init mvebu_armada_pm_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device_node *gpio_ctrl_np;
|
||||
|
|
@ -89,7 +89,7 @@ static int mvebu_armada_xp_gp_pm_init(void)
|
|||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) {
|
||||
for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
|
||||
char *name;
|
||||
struct of_phandle_args args;
|
||||
|
||||
|
|
@ -134,11 +134,19 @@ static int mvebu_armada_xp_gp_pm_init(void)
|
|||
if (!gpio_ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
mvebu_pm_init(mvebu_armada_xp_gp_pm_enter);
|
||||
mvebu_pm_suspend_init(mvebu_armada_pm_enter);
|
||||
|
||||
out:
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
|
||||
late_initcall(mvebu_armada_xp_gp_pm_init);
|
||||
/*
|
||||
* Registering the mvebu_board_pm_enter callback must be done before
|
||||
* the platform_suspend_ops will be registered. In the same time we
|
||||
* also need to have the gpio devices registered. That's why we use a
|
||||
* device_initcall_sync which is called after all the device_initcall
|
||||
* (used by the gpio device) but before the late_initcall (used to
|
||||
* register the platform_suspend_ops)
|
||||
*/
|
||||
device_initcall_sync(mvebu_armada_pm_init);
|
||||
|
|
|
|||
|
|
@ -105,12 +105,10 @@ static phys_addr_t mvebu_internal_reg_base(void)
|
|||
return of_translate_address(np, in_addr);
|
||||
}
|
||||
|
||||
static void mvebu_pm_store_bootinfo(void)
|
||||
static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
|
||||
{
|
||||
u32 *store_addr;
|
||||
phys_addr_t resume_pc;
|
||||
|
||||
store_addr = phys_to_virt(BOOT_INFO_ADDR);
|
||||
resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
|
||||
|
||||
/*
|
||||
|
|
@ -151,14 +149,30 @@ static void mvebu_pm_store_bootinfo(void)
|
|||
writel(BOOT_MAGIC_LIST_END, store_addr);
|
||||
}
|
||||
|
||||
static int mvebu_pm_enter(suspend_state_t state)
|
||||
static int mvebu_pm_store_bootinfo(void)
|
||||
{
|
||||
if (state != PM_SUSPEND_MEM)
|
||||
return -EINVAL;
|
||||
u32 *store_addr;
|
||||
|
||||
store_addr = phys_to_virt(BOOT_INFO_ADDR);
|
||||
|
||||
if (of_machine_is_compatible("marvell,armadaxp"))
|
||||
mvebu_pm_store_armadaxp_bootinfo(store_addr);
|
||||
else
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_enter_suspend(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mvebu_pm_store_bootinfo();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cpu_pm_enter();
|
||||
|
||||
mvebu_pm_store_bootinfo();
|
||||
cpu_suspend(0, mvebu_pm_powerdown);
|
||||
|
||||
outer_resume();
|
||||
|
|
@ -168,23 +182,62 @@ static int mvebu_pm_enter(suspend_state_t state)
|
|||
set_cpu_coherent();
|
||||
|
||||
cpu_pm_exit();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pm_enter(suspend_state_t state)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_SUSPEND_STANDBY:
|
||||
cpu_do_idle();
|
||||
break;
|
||||
case PM_SUSPEND_MEM:
|
||||
pr_warn("Entering suspend to RAM. Only special wake-up sources will resume the system\n");
|
||||
return mvebu_enter_suspend();
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pm_valid(suspend_state_t state)
|
||||
{
|
||||
if (state == PM_SUSPEND_STANDBY)
|
||||
return 1;
|
||||
|
||||
if (state == PM_SUSPEND_MEM && mvebu_board_pm_enter != NULL)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_suspend_ops mvebu_pm_ops = {
|
||||
.enter = mvebu_pm_enter,
|
||||
.valid = suspend_valid_only_mem,
|
||||
.valid = mvebu_pm_valid,
|
||||
};
|
||||
|
||||
int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd))
|
||||
static int __init mvebu_pm_init(void)
|
||||
{
|
||||
if (!of_machine_is_compatible("marvell,armadaxp") &&
|
||||
!of_machine_is_compatible("marvell,armada370") &&
|
||||
!of_machine_is_compatible("marvell,armada380") &&
|
||||
!of_machine_is_compatible("marvell,armada390"))
|
||||
return -ENODEV;
|
||||
|
||||
suspend_set_ops(&mvebu_pm_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
late_initcall(mvebu_pm_init);
|
||||
|
||||
int __init mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,
|
||||
u32 srcmd))
|
||||
{
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
|
||||
if (!of_machine_is_compatible("marvell,armadaxp"))
|
||||
return -ENODEV;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL,
|
||||
"marvell,armada-xp-sdram-controller");
|
||||
if (!np)
|
||||
|
|
@ -212,7 +265,5 @@ int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd))
|
|||
|
||||
mvebu_board_pm_enter = board_pm_enter;
|
||||
|
||||
suspend_set_ops(&mvebu_pm_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
# Makefile for the Linux Kernel SOC specific device drivers.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_MACH_DOVE) += dove/
|
||||
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
||||
obj-$(CONFIG_ARCH_QCOM) += qcom/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
obj-y += pmu.o
|
||||
|
|
@ -0,0 +1,412 @@
|
|||
/*
|
||||
* Marvell Dove PMU support
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/soc/dove/pmu.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define NR_PMU_IRQS 7
|
||||
|
||||
#define PMC_SW_RST 0x30
|
||||
#define PMC_IRQ_CAUSE 0x50
|
||||
#define PMC_IRQ_MASK 0x54
|
||||
|
||||
#define PMU_PWR 0x10
|
||||
#define PMU_ISO 0x58
|
||||
|
||||
struct pmu_data {
|
||||
spinlock_t lock;
|
||||
struct device_node *of_node;
|
||||
void __iomem *pmc_base;
|
||||
void __iomem *pmu_base;
|
||||
struct irq_chip_generic *irq_gc;
|
||||
struct irq_domain *irq_domain;
|
||||
#ifdef CONFIG_RESET_CONTROLLER
|
||||
struct reset_controller_dev reset;
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* The PMU contains a register to reset various subsystems within the
|
||||
* SoC. Export this as a reset controller.
|
||||
*/
|
||||
#ifdef CONFIG_RESET_CONTROLLER
|
||||
#define rcdev_to_pmu(rcdev) container_of(rcdev, struct pmu_data, reset)
|
||||
|
||||
static int pmu_reset_reset(struct reset_controller_dev *rc, unsigned long id)
|
||||
{
|
||||
struct pmu_data *pmu = rcdev_to_pmu(rc);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&pmu->lock, flags);
|
||||
val = readl_relaxed(pmu->pmc_base + PMC_SW_RST);
|
||||
writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST);
|
||||
writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST);
|
||||
spin_unlock_irqrestore(&pmu->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmu_reset_assert(struct reset_controller_dev *rc, unsigned long id)
|
||||
{
|
||||
struct pmu_data *pmu = rcdev_to_pmu(rc);
|
||||
unsigned long flags;
|
||||
u32 val = ~BIT(id);
|
||||
|
||||
spin_lock_irqsave(&pmu->lock, flags);
|
||||
val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
|
||||
writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
|
||||
spin_unlock_irqrestore(&pmu->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmu_reset_deassert(struct reset_controller_dev *rc, unsigned long id)
|
||||
{
|
||||
struct pmu_data *pmu = rcdev_to_pmu(rc);
|
||||
unsigned long flags;
|
||||
u32 val = BIT(id);
|
||||
|
||||
spin_lock_irqsave(&pmu->lock, flags);
|
||||
val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
|
||||
writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
|
||||
spin_unlock_irqrestore(&pmu->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct reset_control_ops pmu_reset_ops = {
|
||||
.reset = pmu_reset_reset,
|
||||
.assert = pmu_reset_assert,
|
||||
.deassert = pmu_reset_deassert,
|
||||
};
|
||||
|
||||
static struct reset_controller_dev pmu_reset __initdata = {
|
||||
.ops = &pmu_reset_ops,
|
||||
.owner = THIS_MODULE,
|
||||
.nr_resets = 32,
|
||||
};
|
||||
|
||||
static void __init pmu_reset_init(struct pmu_data *pmu)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pmu->reset = pmu_reset;
|
||||
pmu->reset.of_node = pmu->of_node;
|
||||
|
||||
ret = reset_controller_register(&pmu->reset);
|
||||
if (ret)
|
||||
pr_err("pmu: %s failed: %d\n", "reset_controller_register", ret);
|
||||
}
|
||||
#else
|
||||
static void __init pmu_reset_init(struct pmu_data *pmu)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
struct pmu_domain {
|
||||
struct pmu_data *pmu;
|
||||
u32 pwr_mask;
|
||||
u32 rst_mask;
|
||||
u32 iso_mask;
|
||||
struct generic_pm_domain base;
|
||||
};
|
||||
|
||||
#define to_pmu_domain(dom) container_of(dom, struct pmu_domain, base)
|
||||
|
||||
/*
|
||||
* This deals with the "old" Marvell sequence of bringing a power domain
|
||||
* down/up, which is: apply power, release reset, disable isolators.
|
||||
*
|
||||
* Later devices apparantly use a different sequence: power up, disable
|
||||
* isolators, assert repair signal, enable SRMA clock, enable AXI clock,
|
||||
* enable module clock, deassert reset.
|
||||
*
|
||||
* Note: reading the assembly, it seems that the IO accessors have an
|
||||
* unfortunate side-effect - they cause memory already read into registers
|
||||
* for the if () to be re-read for the bit-set or bit-clear operation.
|
||||
* The code is written to avoid this.
|
||||
*/
|
||||
static int pmu_domain_power_off(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct pmu_domain *pmu_dom = to_pmu_domain(domain);
|
||||
struct pmu_data *pmu = pmu_dom->pmu;
|
||||
unsigned long flags;
|
||||
unsigned int val;
|
||||
void __iomem *pmu_base = pmu->pmu_base;
|
||||
void __iomem *pmc_base = pmu->pmc_base;
|
||||
|
||||
spin_lock_irqsave(&pmu->lock, flags);
|
||||
|
||||
/* Enable isolators */
|
||||
if (pmu_dom->iso_mask) {
|
||||
val = ~pmu_dom->iso_mask;
|
||||
val &= readl_relaxed(pmu_base + PMU_ISO);
|
||||
writel_relaxed(val, pmu_base + PMU_ISO);
|
||||
}
|
||||
|
||||
/* Reset unit */
|
||||
if (pmu_dom->rst_mask) {
|
||||
val = ~pmu_dom->rst_mask;
|
||||
val &= readl_relaxed(pmc_base + PMC_SW_RST);
|
||||
writel_relaxed(val, pmc_base + PMC_SW_RST);
|
||||
}
|
||||
|
||||
/* Power down */
|
||||
val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask;
|
||||
writel_relaxed(val, pmu_base + PMU_PWR);
|
||||
|
||||
spin_unlock_irqrestore(&pmu->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmu_domain_power_on(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct pmu_domain *pmu_dom = to_pmu_domain(domain);
|
||||
struct pmu_data *pmu = pmu_dom->pmu;
|
||||
unsigned long flags;
|
||||
unsigned int val;
|
||||
void __iomem *pmu_base = pmu->pmu_base;
|
||||
void __iomem *pmc_base = pmu->pmc_base;
|
||||
|
||||
spin_lock_irqsave(&pmu->lock, flags);
|
||||
|
||||
/* Power on */
|
||||
val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR);
|
||||
writel_relaxed(val, pmu_base + PMU_PWR);
|
||||
|
||||
/* Release reset */
|
||||
if (pmu_dom->rst_mask) {
|
||||
val = pmu_dom->rst_mask;
|
||||
val |= readl_relaxed(pmc_base + PMC_SW_RST);
|
||||
writel_relaxed(val, pmc_base + PMC_SW_RST);
|
||||
}
|
||||
|
||||
/* Disable isolators */
|
||||
if (pmu_dom->iso_mask) {
|
||||
val = pmu_dom->iso_mask;
|
||||
val |= readl_relaxed(pmu_base + PMU_ISO);
|
||||
writel_relaxed(val, pmu_base + PMU_ISO);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&pmu->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __pmu_domain_register(struct pmu_domain *domain,
|
||||
struct device_node *np)
|
||||
{
|
||||
unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR);
|
||||
|
||||
domain->base.power_off = pmu_domain_power_off;
|
||||
domain->base.power_on = pmu_domain_power_on;
|
||||
|
||||
pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask));
|
||||
|
||||
if (np)
|
||||
of_genpd_add_provider_simple(np, &domain->base);
|
||||
}
|
||||
|
||||
/* PMU IRQ controller */
|
||||
static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct pmu_data *pmu = irq_get_handler_data(irq);
|
||||
struct irq_chip_generic *gc = pmu->irq_gc;
|
||||
struct irq_domain *domain = pmu->irq_domain;
|
||||
void __iomem *base = gc->reg_base;
|
||||
u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache;
|
||||
u32 done = ~0;
|
||||
|
||||
if (stat == 0) {
|
||||
handle_bad_irq(irq, desc);
|
||||
return;
|
||||
}
|
||||
|
||||
while (stat) {
|
||||
u32 hwirq = fls(stat) - 1;
|
||||
|
||||
stat &= ~(1 << hwirq);
|
||||
done &= ~(1 << hwirq);
|
||||
|
||||
generic_handle_irq(irq_find_mapping(domain, hwirq));
|
||||
}
|
||||
|
||||
/*
|
||||
* The PMU mask register is not RW0C: it is RW. This means that
|
||||
* the bits take whatever value is written to them; if you write
|
||||
* a '1', you will set the interrupt.
|
||||
*
|
||||
* Unfortunately this means there is NO race free way to clear
|
||||
* these interrupts.
|
||||
*
|
||||
* So, let's structure the code so that the window is as small as
|
||||
* possible.
|
||||
*/
|
||||
irq_gc_lock(gc);
|
||||
done &= readl_relaxed(base + PMC_IRQ_CAUSE);
|
||||
writel_relaxed(done, base + PMC_IRQ_CAUSE);
|
||||
irq_gc_unlock(gc);
|
||||
}
|
||||
|
||||
static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
|
||||
{
|
||||
const char *name = "pmu_irq";
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_domain *domain;
|
||||
int ret;
|
||||
|
||||
/* mask and clear all interrupts */
|
||||
writel(0, pmu->pmc_base + PMC_IRQ_MASK);
|
||||
writel(0, pmu->pmc_base + PMC_IRQ_CAUSE);
|
||||
|
||||
domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS,
|
||||
&irq_generic_chip_ops, NULL);
|
||||
if (!domain) {
|
||||
pr_err("%s: unable to add irq domain\n", name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(domain, NR_PMU_IRQS, 1, name,
|
||||
handle_level_irq,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE, 0,
|
||||
IRQ_GC_INIT_MASK_CACHE);
|
||||
if (ret) {
|
||||
pr_err("%s: unable to alloc irq domain gc: %d\n", name, ret);
|
||||
irq_domain_remove(domain);
|
||||
return ret;
|
||||
}
|
||||
|
||||
gc = irq_get_domain_generic_chip(domain, 0);
|
||||
gc->reg_base = pmu->pmc_base;
|
||||
gc->chip_types[0].regs.mask = PMC_IRQ_MASK;
|
||||
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
|
||||
pmu->irq_domain = domain;
|
||||
pmu->irq_gc = gc;
|
||||
|
||||
irq_set_handler_data(irq, pmu);
|
||||
irq_set_chained_handler(irq, pmu_irq_handler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* pmu: power-manager@d0000 {
|
||||
* compatible = "marvell,dove-pmu";
|
||||
* reg = <0xd0000 0x8000> <0xd8000 0x8000>;
|
||||
* interrupts = <33>;
|
||||
* interrupt-controller;
|
||||
* #reset-cells = 1;
|
||||
* vpu_domain: vpu-domain {
|
||||
* #power-domain-cells = <0>;
|
||||
* marvell,pmu_pwr_mask = <0x00000008>;
|
||||
* marvell,pmu_iso_mask = <0x00000001>;
|
||||
* resets = <&pmu 16>;
|
||||
* };
|
||||
* gpu_domain: gpu-domain {
|
||||
* #power-domain-cells = <0>;
|
||||
* marvell,pmu_pwr_mask = <0x00000004>;
|
||||
* marvell,pmu_iso_mask = <0x00000002>;
|
||||
* resets = <&pmu 18>;
|
||||
* };
|
||||
* };
|
||||
*/
|
||||
int __init dove_init_pmu(void)
|
||||
{
|
||||
struct device_node *np_pmu, *domains_node, *np;
|
||||
struct pmu_data *pmu;
|
||||
int ret, parent_irq;
|
||||
|
||||
/* Lookup the PMU node */
|
||||
np_pmu = of_find_compatible_node(NULL, NULL, "marvell,dove-pmu");
|
||||
if (!np_pmu)
|
||||
return 0;
|
||||
|
||||
domains_node = of_get_child_by_name(np_pmu, "domains");
|
||||
if (!domains_node) {
|
||||
pr_err("%s: failed to find domains sub-node\n", np_pmu->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
|
||||
if (!pmu)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&pmu->lock);
|
||||
pmu->of_node = np_pmu;
|
||||
pmu->pmc_base = of_iomap(pmu->of_node, 0);
|
||||
pmu->pmu_base = of_iomap(pmu->of_node, 1);
|
||||
if (!pmu->pmc_base || !pmu->pmu_base) {
|
||||
pr_err("%s: failed to map PMU\n", np_pmu->name);
|
||||
iounmap(pmu->pmu_base);
|
||||
iounmap(pmu->pmc_base);
|
||||
kfree(pmu);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pmu_reset_init(pmu);
|
||||
|
||||
for_each_available_child_of_node(domains_node, np) {
|
||||
struct of_phandle_args args;
|
||||
struct pmu_domain *domain;
|
||||
|
||||
domain = kzalloc(sizeof(*domain), GFP_KERNEL);
|
||||
if (!domain)
|
||||
break;
|
||||
|
||||
domain->pmu = pmu;
|
||||
domain->base.name = kstrdup(np->name, GFP_KERNEL);
|
||||
if (!domain->base.name) {
|
||||
kfree(domain);
|
||||
break;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "marvell,pmu_pwr_mask",
|
||||
&domain->pwr_mask);
|
||||
of_property_read_u32(np, "marvell,pmu_iso_mask",
|
||||
&domain->iso_mask);
|
||||
|
||||
/*
|
||||
* We parse the reset controller property directly here
|
||||
* to ensure that we can operate when the reset controller
|
||||
* support is not configured into the kernel.
|
||||
*/
|
||||
ret = of_parse_phandle_with_args(np, "resets", "#reset-cells",
|
||||
0, &args);
|
||||
if (ret == 0) {
|
||||
if (args.np == pmu->of_node)
|
||||
domain->rst_mask = BIT(args.args[0]);
|
||||
of_node_put(args.np);
|
||||
}
|
||||
|
||||
__pmu_domain_register(domain, np);
|
||||
}
|
||||
pm_genpd_poweroff_unused();
|
||||
|
||||
/* Loss of the interrupt controller is not a fatal error. */
|
||||
parent_irq = irq_of_parse_and_map(pmu->of_node, 0);
|
||||
if (!parent_irq) {
|
||||
pr_err("%s: no interrupt specified\n", np_pmu->name);
|
||||
} else {
|
||||
ret = dove_init_pmu_irq(pmu, parent_irq);
|
||||
if (ret)
|
||||
pr_err("dove_init_pmu_irq() failed: %d\n", ret);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef LINUX_SOC_DOVE_PMU_H
|
||||
#define LINUX_SOC_DOVE_PMU_H
|
||||
|
||||
int dove_init_pmu(void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue