misc: rtsx: Use pcie_capability_clear_and_set_word() for PCI_EXP_LNKCTL
Instead of using the driver-specific rtsx_pci_update_cfg_byte() to update the PCIe Link Control Register, use pcie_capability_clear_and_set_word() like the rest of the kernel does. This makes it easier to maintain ASPM across the PCI core and drivers. Remove the now-unused rtsx_pci_update_cfg_byte() and ASPM_MASK_NEG definitions. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20200521180545.1159896-5-helgaas@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -349,15 +349,12 @@ static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)
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{
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u8 val = 0;
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if (pcr->aspm_enabled == enable)
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return;
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if (enable)
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val = pcr->aspm_en;
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rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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ASPM_MASK_NEG, val);
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pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC,
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enable ? pcr->aspm_en : 0);
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pcr->aspm_enabled = enable;
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}
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@ -572,15 +572,12 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
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static void rts5260_set_aspm(struct rtsx_pcr *pcr, bool enable)
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{
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u8 val = 0;
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if (pcr->aspm_enabled == enable)
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return;
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if (enable)
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val = pcr->aspm_en;
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rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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ASPM_MASK_NEG, val);
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pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC,
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enable ? pcr->aspm : 0);
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pcr->aspm_enabled = enable;
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}
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@ -518,28 +518,22 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
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static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
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{
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u8 val = 0;
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if (pcr->aspm_enabled == enable)
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return;
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val = pcr->aspm_en;
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rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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ASPM_MASK_NEG, val);
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pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
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pcr->aspm_enabled = enable;
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}
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static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
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{
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u8 val = 0;
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if (pcr->aspm_enabled == enable)
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return;
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val = 0;
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rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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ASPM_MASK_NEG, val);
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pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC, 0);
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rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
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udelay(10);
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pcr->aspm_enabled = enable;
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@ -57,14 +57,14 @@ MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
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static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
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{
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rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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ASPM_MASK_NEG, pcr->aspm_en);
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pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
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}
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static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
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{
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rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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ASPM_MASK_NEG, 0);
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pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC, 0);
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}
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static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
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@ -29,7 +29,6 @@
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#define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
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#define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
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#define CMD_TIMEOUT_DEF 100
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#define ASPM_MASK_NEG 0xFC
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#define MASK_8_BIT_DEF 0xFF
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#define SSC_CLOCK_STABLE_WAIT 130
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@ -1307,18 +1307,6 @@ static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
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return (u8 *)(pcr->host_cmds_ptr);
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}
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static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
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u8 mask, u8 append)
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{
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int err;
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u8 val;
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err = pci_read_config_byte(pcr->pci, addr, &val);
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if (err < 0)
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return err;
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return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
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}
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static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
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{
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24);
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