net: dsa: qca8k: move qca8k_setup()
Move qca8k_setup() to be later in the file to avoid needing prototypes for called functions. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King (Oracle)
David S. Miller
parent
bde018222c
commit
3ce855f040
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@ -1632,220 +1632,6 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
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return 0;
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}
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static int
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qca8k_setup(struct dsa_switch *ds)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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int cpu_port, ret, i;
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u32 mask;
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cpu_port = qca8k_find_cpu_port(ds);
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if (cpu_port < 0) {
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dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
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return cpu_port;
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}
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/* Parse CPU port config to be later used in phy_link mac_config */
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ret = qca8k_parse_port_config(priv);
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if (ret)
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return ret;
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ret = qca8k_setup_mdio_bus(priv);
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if (ret)
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return ret;
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ret = qca8k_setup_of_pws_reg(priv);
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if (ret)
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return ret;
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ret = qca8k_setup_mac_pwr_sel(priv);
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if (ret)
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return ret;
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/* Make sure MAC06 is disabled */
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ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
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QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
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if (ret) {
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dev_err(priv->dev, "failed disabling MAC06 exchange");
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return ret;
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}
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/* Enable CPU Port */
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ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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if (ret) {
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dev_err(priv->dev, "failed enabling CPU port");
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return ret;
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}
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/* Enable MIB counters */
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ret = qca8k_mib_init(priv);
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if (ret)
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dev_warn(priv->dev, "mib init failed");
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/* Initial setup of all ports */
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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/* Disable forwarding by default on all ports */
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER, 0);
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if (ret)
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return ret;
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/* Enable QCA header mode on all cpu ports */
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if (dsa_is_cpu_port(ds, i)) {
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ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
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FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
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FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
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if (ret) {
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dev_err(priv->dev, "failed enabling QCA header mode");
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return ret;
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}
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}
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/* Disable MAC by default on all user ports */
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if (dsa_is_user_port(ds, i))
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qca8k_port_set_status(priv, i, 0);
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}
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/* Forward all unknown frames to CPU port for Linux processing
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* Notice that in multi-cpu config only one port should be set
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* for igmp, unknown, multicast and broadcast packet
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*/
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ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
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if (ret)
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return ret;
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/* Setup connection between CPU port & user ports
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* Configure specific switch configuration for ports
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*/
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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/* CPU port gets connected to all user ports of the switch */
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if (dsa_is_cpu_port(ds, i)) {
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
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if (ret)
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return ret;
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}
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/* Individual user ports get connected to CPU port only */
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if (dsa_is_user_port(ds, i)) {
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER,
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BIT(cpu_port));
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if (ret)
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return ret;
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/* Enable ARP Auto-learning by default */
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ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_LEARN);
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if (ret)
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return ret;
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/* For port based vlans to work we need to set the
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* default egress vid
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*/
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ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
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QCA8K_EGREES_VLAN_PORT_MASK(i),
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QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
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if (ret)
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return ret;
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ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
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QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
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QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
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if (ret)
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return ret;
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}
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/* The port 5 of the qca8337 have some problem in flood condition. The
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* original legacy driver had some specific buffer and priority settings
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* for the different port suggested by the QCA switch team. Add this
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* missing settings to improve switch stability under load condition.
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* This problem is limited to qca8337 and other qca8k switch are not affected.
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*/
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if (priv->switch_id == QCA8K_ID_QCA8337) {
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switch (i) {
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/* The 2 CPU port and port 5 requires some different
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* priority than any other ports.
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*/
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case 0:
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case 5:
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case 6:
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mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
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QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
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break;
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default:
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mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
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QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
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}
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qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
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mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
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QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_WRED_EN;
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qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
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QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
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QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_WRED_EN,
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mask);
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}
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/* Set initial MTU for every port.
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* We have only have a general MTU setting. So track
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* every port and set the max across all port.
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* Set per port MTU to 1500 as the MTU change function
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* will add the overhead and if its set to 1518 then it
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* will apply the overhead again and we will end up with
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* MTU of 1536 instead of 1518
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*/
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priv->port_mtu[i] = ETH_DATA_LEN;
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}
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/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
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if (priv->switch_id == QCA8K_ID_QCA8327) {
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mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
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QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
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qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
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QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
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QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
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mask);
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}
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/* Setup our port MTUs to match power on defaults */
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ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
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if (ret)
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dev_warn(priv->dev, "failed setting MTU settings");
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/* Flush the FDB table */
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qca8k_fdb_flush(priv);
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/* We don't have interrupts for link changes, so we need to poll */
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ds->pcs_poll = true;
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/* Set min a max ageing value supported */
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ds->ageing_time_min = 7000;
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ds->ageing_time_max = 458745000;
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/* Set max number of LAGs supported */
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ds->num_lag_ids = QCA8K_NUM_LAGS;
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return 0;
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}
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static void
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qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
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u32 reg)
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@ -2990,6 +2776,220 @@ static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
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return 0;
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}
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static int
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qca8k_setup(struct dsa_switch *ds)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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int cpu_port, ret, i;
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u32 mask;
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cpu_port = qca8k_find_cpu_port(ds);
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if (cpu_port < 0) {
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dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
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return cpu_port;
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}
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/* Parse CPU port config to be later used in phy_link mac_config */
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ret = qca8k_parse_port_config(priv);
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if (ret)
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return ret;
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ret = qca8k_setup_mdio_bus(priv);
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if (ret)
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return ret;
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ret = qca8k_setup_of_pws_reg(priv);
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if (ret)
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return ret;
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ret = qca8k_setup_mac_pwr_sel(priv);
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if (ret)
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return ret;
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/* Make sure MAC06 is disabled */
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ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
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QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
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if (ret) {
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dev_err(priv->dev, "failed disabling MAC06 exchange");
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return ret;
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}
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/* Enable CPU Port */
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ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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if (ret) {
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dev_err(priv->dev, "failed enabling CPU port");
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return ret;
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}
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/* Enable MIB counters */
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ret = qca8k_mib_init(priv);
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if (ret)
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dev_warn(priv->dev, "mib init failed");
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/* Initial setup of all ports */
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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/* Disable forwarding by default on all ports */
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER, 0);
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if (ret)
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return ret;
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/* Enable QCA header mode on all cpu ports */
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if (dsa_is_cpu_port(ds, i)) {
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ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
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FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
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FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
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if (ret) {
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dev_err(priv->dev, "failed enabling QCA header mode");
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return ret;
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}
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}
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/* Disable MAC by default on all user ports */
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if (dsa_is_user_port(ds, i))
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qca8k_port_set_status(priv, i, 0);
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}
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/* Forward all unknown frames to CPU port for Linux processing
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* Notice that in multi-cpu config only one port should be set
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* for igmp, unknown, multicast and broadcast packet
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*/
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ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
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FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
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if (ret)
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return ret;
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/* Setup connection between CPU port & user ports
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* Configure specific switch configuration for ports
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*/
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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/* CPU port gets connected to all user ports of the switch */
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if (dsa_is_cpu_port(ds, i)) {
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
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if (ret)
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return ret;
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}
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/* Individual user ports get connected to CPU port only */
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if (dsa_is_user_port(ds, i)) {
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER,
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BIT(cpu_port));
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if (ret)
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return ret;
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/* Enable ARP Auto-learning by default */
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ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_LEARN);
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if (ret)
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return ret;
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/* For port based vlans to work we need to set the
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* default egress vid
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*/
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ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
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QCA8K_EGREES_VLAN_PORT_MASK(i),
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QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
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if (ret)
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return ret;
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ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
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QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
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QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
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if (ret)
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return ret;
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}
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/* The port 5 of the qca8337 have some problem in flood condition. The
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* original legacy driver had some specific buffer and priority settings
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* for the different port suggested by the QCA switch team. Add this
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* missing settings to improve switch stability under load condition.
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* This problem is limited to qca8337 and other qca8k switch are not affected.
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*/
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if (priv->switch_id == QCA8K_ID_QCA8337) {
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switch (i) {
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/* The 2 CPU port and port 5 requires some different
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* priority than any other ports.
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*/
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case 0:
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case 5:
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case 6:
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mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
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QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
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break;
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default:
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mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
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QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
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QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
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}
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qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
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mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
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QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_WRED_EN;
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qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
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QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
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QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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QCA8K_PORT_HOL_CTRL1_WRED_EN,
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mask);
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}
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/* Set initial MTU for every port.
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* We have only have a general MTU setting. So track
|
||||
* every port and set the max across all port.
|
||||
* Set per port MTU to 1500 as the MTU change function
|
||||
* will add the overhead and if its set to 1518 then it
|
||||
* will apply the overhead again and we will end up with
|
||||
* MTU of 1536 instead of 1518
|
||||
*/
|
||||
priv->port_mtu[i] = ETH_DATA_LEN;
|
||||
}
|
||||
|
||||
/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
|
||||
if (priv->switch_id == QCA8K_ID_QCA8327) {
|
||||
mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
|
||||
QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
|
||||
qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
|
||||
QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
|
||||
QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
|
||||
mask);
|
||||
}
|
||||
|
||||
/* Setup our port MTUs to match power on defaults */
|
||||
ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
|
||||
if (ret)
|
||||
dev_warn(priv->dev, "failed setting MTU settings");
|
||||
|
||||
/* Flush the FDB table */
|
||||
qca8k_fdb_flush(priv);
|
||||
|
||||
/* We don't have interrupts for link changes, so we need to poll */
|
||||
ds->pcs_poll = true;
|
||||
|
||||
/* Set min a max ageing value supported */
|
||||
ds->ageing_time_min = 7000;
|
||||
ds->ageing_time_max = 458745000;
|
||||
|
||||
/* Set max number of LAGs supported */
|
||||
ds->num_lag_ids = QCA8K_NUM_LAGS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dsa_switch_ops qca8k_switch_ops = {
|
||||
.get_tag_protocol = qca8k_get_tag_protocol,
|
||||
.setup = qca8k_setup,
|
||||
|
|
|
|||
Loading…
Reference in New Issue