Raw NAND changes:
- jz4740: fix a compilation warning - fsmc: fix a regression introduced by ->select_chip() deprecation - denali: fix a regression introduced by NAND_KEEP_TIMINGS addition -----BEGIN PGP SIGNATURE----- iQJKBAABCgA0FiEEKmCqpbOU668PNA69Ze02AX4ItwAFAlxBzC4WHGJicmV6aWxs b25Aa2VybmVsLm9yZwAKCRBl7TYBfgi3AByyD/9geVQxQ9U2buSRxtjQ6TYggkwI N8Dc5r1SmILmAtZTm0G3TpH2gibx+BOfajtjRkR9LKbji9tLo+DV7acrBz7ezQrO rzAf0hvLIG/lfexvU23JrszG0TOPFZm0diitRgeZn+bSih6PTjUswPhJHy3WqFjt 4bpPCofdCwRaQfORZ+yqMyTdE1t4hRNQ31Uk8vjtZQdkN0ROmV7OvfzvNHK3/4oL N6OEZCIy0nJS9+x7Kv7j/EpIVUad/MddTShC1HRrxClcbnlerrA/X3vn+2L7U8Qr l53YDBBNNnuKYjJRU6qUtipS6OC5JUeAQV4Wd9vRJyQXwHRf1Ti6UlgVIosoIFSr lWJaMuDXSt+ruHEym/UAEXFzFwU4E3Mek0Tu86/TH7MSs3te0cPhGXhxhM/VzyKy a3zVMBeYk+Itqzv9KjSth0T7jwcgQpDtVbdR2YI8b+rSmfifenCXHIIctjDRt0XM s/AwoWbwIV+x7/NEHY/Sex5PNyD1acLSYv42eVnFaKh8AlFHe73qqeuSIcm/4PdQ R7tjPmHfhiGC8wzbHWlaz05aqZa8q0X0576q3YqYV0WPWE/0BbQlI2uREPLnYyao OG1Etx27owXekOWXtEpTOBcgl32qcOjNguf2TO/W+z0HTwtc4sFy5zTGPBA9cUZ/ 2rZ+FMubCdqqXqYJzg== =qyZu -----END PGP SIGNATURE----- Merge tag 'mtd/fixes-for-5.0-rc3' of git://git.infradead.org/linux-mtd Pull mtd fixes from Boris Brezillon: "Raw NAND changes: - jz4740: fix a compilation warning - fsmc: fix a regression introduced by ->select_chip() deprecation - denali: fix a regression introduced by NAND_KEEP_TIMINGS addition" * tag 'mtd/fixes-for-5.0-rc3' of git://git.infradead.org/linux-mtd: mtd: rawnand: denali: get ->setup_data_interface() working again mtd: nand: jz4740: fix '__iomem *' vs. '* __iomem' mtd: rawnand: fsmc: Keep bank enable bit set
This commit is contained in:
commit
3cdf680ea1
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@ -1322,7 +1322,7 @@ int denali_init(struct denali_nand_info *denali)
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}
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}
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/* clk rate info is needed for setup_data_interface */
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/* clk rate info is needed for setup_data_interface */
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if (denali->clk_rate && denali->clk_x_rate)
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if (!denali->clk_rate || !denali->clk_x_rate)
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chip->options |= NAND_KEEP_TIMINGS;
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chip->options |= NAND_KEEP_TIMINGS;
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chip->legacy.dummy_controller.ops = &denali_controller_ops;
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chip->legacy.dummy_controller.ops = &denali_controller_ops;
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@ -593,23 +593,6 @@ static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
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dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
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dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
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}
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}
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/* fsmc_select_chip - assert or deassert nCE */
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static void fsmc_ce_ctrl(struct fsmc_nand_data *host, bool assert)
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{
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u32 pc = readl(host->regs_va + FSMC_PC);
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if (!assert)
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writel_relaxed(pc & ~FSMC_ENABLE, host->regs_va + FSMC_PC);
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else
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writel_relaxed(pc | FSMC_ENABLE, host->regs_va + FSMC_PC);
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/*
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* nCE line changes must be applied before returning from this
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* function.
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*/
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mb();
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}
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/*
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/*
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* fsmc_exec_op - hook called by the core to execute NAND operations
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* fsmc_exec_op - hook called by the core to execute NAND operations
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*
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*
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@ -627,8 +610,6 @@ static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
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pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
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pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
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fsmc_ce_ctrl(host, true);
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for (op_id = 0; op_id < op->ninstrs; op_id++) {
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for (op_id = 0; op_id < op->ninstrs; op_id++) {
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instr = &op->instrs[op_id];
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instr = &op->instrs[op_id];
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@ -686,8 +667,6 @@ static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
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}
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}
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}
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}
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fsmc_ce_ctrl(host, false);
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return ret;
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return ret;
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}
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}
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@ -260,7 +260,7 @@ static int jz_nand_correct_ecc_rs(struct nand_chip *chip, uint8_t *dat,
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}
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}
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static int jz_nand_ioremap_resource(struct platform_device *pdev,
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static int jz_nand_ioremap_resource(struct platform_device *pdev,
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const char *name, struct resource **res, void *__iomem *base)
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const char *name, struct resource **res, void __iomem **base)
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{
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{
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int ret;
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int ret;
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