staging: hikey9xx: hi6421-spmi-pmic: document registers
Make it clearer about how the IRQ registers are filled by adding a table with them, with two macros used to calculate the mask register. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/10f52ec0a8346fb883245344886c44714c859cd1.1611949675.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -38,10 +38,6 @@ enum hi6421_spmi_pmic_irq_list {
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#define HISI_IRQ_ARRAY 2
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#define HISI_IRQ_NUM (HISI_IRQ_ARRAY * 8)
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#define HISI_IRQ_MASK GENMASK(1, 0)
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#define SOC_PMIC_IRQ_MASK_0_ADDR 0x0202
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#define SOC_PMIC_IRQ0_ADDR 0x0212
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#define HISI_IRQ_KEY_NUM 0
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@ -49,6 +45,36 @@ enum hi6421_spmi_pmic_irq_list {
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#define HISI_IRQ_KEY_VALUE (BIT(POWERKEY_DOWN) | BIT(POWERKEY_UP))
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#define HISI_MASK GENMASK(HISI_BITS - 1, 0)
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/*
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* The IRQs are mapped as:
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*
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* ====================== ============= ============ =====
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* IRQ MASK REGISTER IRQ REGISTER BIT
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* ====================== ============= ============ =====
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* OTMP 0x0202 0x212 bit 0
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* VBUS_CONNECT 0x0202 0x212 bit 1
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* VBUS_DISCONNECT 0x0202 0x212 bit 2
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* ALARMON_R 0x0202 0x212 bit 3
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* HOLD_6S 0x0202 0x212 bit 4
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* HOLD_1S 0x0202 0x212 bit 5
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* POWERKEY_UP 0x0202 0x212 bit 6
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* POWERKEY_DOWN 0x0202 0x212 bit 7
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*
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* OCP_SCP_R 0x0203 0x213 bit 0
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* COUL_R 0x0203 0x213 bit 1
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* SIM0_HPD_R 0x0203 0x213 bit 2
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* SIM0_HPD_F 0x0203 0x213 bit 3
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* SIM1_HPD_R 0x0203 0x213 bit 4
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* SIM1_HPD_F 0x0203 0x213 bit 5
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* ====================== ============= ============ =====
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*/
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#define SOC_PMIC_IRQ_MASK_0_ADDR 0x0202
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#define SOC_PMIC_IRQ0_ADDR 0x0212
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#define IRQ_MASK_REGISTER(irq_data) (SOC_PMIC_IRQ_MASK_0_ADDR + \
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(irqd_to_hwirq(irq_data) >> 3))
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#define IRQ_MASK_BIT(irq_data) BIT(irqd_to_hwirq(irq_data) & 0x07)
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static const struct mfd_cell hi6421v600_devs[] = {
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{ .name = "hi6421v600-regulator", },
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};
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@ -89,13 +115,12 @@ static void hi6421_spmi_irq_mask(struct irq_data *d)
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unsigned int data;
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u32 offset;
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offset = (irqd_to_hwirq(d) >> HISI_IRQ_MASK);
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offset += SOC_PMIC_IRQ_MASK_0_ADDR;
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offset = IRQ_MASK_REGISTER(d);
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spin_lock_irqsave(&ddata->lock, flags);
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regmap_read(ddata->regmap, offset, &data);
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data |= (1 << (irqd_to_hwirq(d) & 0x07));
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data |= IRQ_MASK_BIT(d);
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regmap_write(ddata->regmap, offset, data);
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spin_unlock_irqrestore(&ddata->lock, flags);
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