rtc: pm8xxx: add support for nvmem offset
On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which the driver can take into account. Add support for storing a 32-bit offset from the Epoch in an nvmem cell so that the RTC time can be set on such platforms. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230202155448.6715-18-johan+linaro@kernel.org Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Johan Hovold
Alexandre Belloni
parent
430aa33a30
commit
3ca04951b0
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@ -1,8 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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/*
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* pm8xxx RTC driver
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/init.h>
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#include <linux/rtc.h>
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#include <linux/platform_device.h>
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@ -49,6 +54,8 @@ struct pm8xxx_rtc_regs {
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* @alarm_irq: alarm irq number
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* @regs: register description
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* @dev: device structure
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* @nvmem_cell: nvmem cell for offset
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* @offset: offset from epoch in seconds
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*/
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struct pm8xxx_rtc {
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struct rtc_device *rtc;
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@ -57,8 +64,60 @@ struct pm8xxx_rtc {
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int alarm_irq;
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const struct pm8xxx_rtc_regs *regs;
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struct device *dev;
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struct nvmem_cell *nvmem_cell;
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u32 offset;
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};
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static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd)
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{
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size_t len;
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void *buf;
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int rc;
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buf = nvmem_cell_read(rtc_dd->nvmem_cell, &len);
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if (IS_ERR(buf)) {
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rc = PTR_ERR(buf);
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dev_dbg(rtc_dd->dev, "failed to read nvmem offset: %d\n", rc);
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return rc;
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}
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if (len != sizeof(u32)) {
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dev_dbg(rtc_dd->dev, "unexpected nvmem cell size %zu\n", len);
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kfree(buf);
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return -EINVAL;
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}
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rtc_dd->offset = get_unaligned_le32(buf);
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kfree(buf);
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return 0;
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}
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static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
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{
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u8 buf[sizeof(u32)];
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int rc;
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put_unaligned_le32(offset, buf);
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rc = nvmem_cell_write(rtc_dd->nvmem_cell, buf, sizeof(buf));
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if (rc < 0) {
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dev_dbg(rtc_dd->dev, "failed to write nvmem offset: %d\n", rc);
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return rc;
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}
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return 0;
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}
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static int pm8xxx_rtc_read_offset(struct pm8xxx_rtc *rtc_dd)
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{
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if (!rtc_dd->nvmem_cell)
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return 0;
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return pm8xxx_rtc_read_nvmem_offset(rtc_dd);
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}
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static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
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{
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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@ -90,6 +149,33 @@ static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
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return 0;
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}
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static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs)
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{
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u32 raw_secs;
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u32 offset;
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int rc;
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if (!rtc_dd->nvmem_cell)
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return -ENODEV;
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rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs);
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if (rc)
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return rc;
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offset = secs - raw_secs;
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if (offset == rtc_dd->offset)
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return 0;
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rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);
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if (rc)
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return rc;
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rtc_dd->offset = offset;
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return 0;
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}
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/*
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* Steps to write the RTC registers.
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* 1. Disable alarm if enabled.
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@ -99,23 +185,15 @@ static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
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* 5. Enable rtc if disabled in step 2.
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* 6. Enable alarm if disabled in step 1.
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*/
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static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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static int __pm8xxx_rtc_set_time(struct pm8xxx_rtc *rtc_dd, u32 secs)
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{
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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u8 value[NUM_8_BIT_RTC_REGS];
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bool alarm_enabled;
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u32 secs;
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int rc;
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if (!rtc_dd->allow_set_time)
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return -ENODEV;
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secs = rtc_tm_to_time64(tm);
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put_unaligned_le32(secs, value);
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dev_dbg(dev, "set time: %ptRd %ptRt (%u)\n", tm, tm, secs);
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rc = regmap_update_bits_check(rtc_dd->regmap, regs->alarm_ctrl,
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regs->alarm_en, 0, &alarm_enabled);
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if (rc)
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@ -158,6 +236,27 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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return 0;
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}
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static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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u32 secs;
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int rc;
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secs = rtc_tm_to_time64(tm);
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if (rtc_dd->allow_set_time)
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rc = __pm8xxx_rtc_set_time(rtc_dd, secs);
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else
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rc = pm8xxx_rtc_update_offset(rtc_dd, secs);
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if (rc)
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return rc;
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dev_dbg(dev, "set time: %ptRd %ptRt (%u + %u)\n", tm, tm,
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secs - rtc_dd->offset, rtc_dd->offset);
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return 0;
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}
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static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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@ -168,10 +267,11 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
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if (rc)
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return rc;
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secs += rtc_dd->offset;
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rtc_time64_to_tm(secs, tm);
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dev_dbg(dev, "read time: %ptRd %ptRt (%u)\n", tm, tm, secs);
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dev_dbg(dev, "read time: %ptRd %ptRt (%u + %u)\n", tm, tm,
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secs - rtc_dd->offset, rtc_dd->offset);
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return 0;
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}
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@ -184,6 +284,7 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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int rc;
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secs = rtc_tm_to_time64(&alarm->time);
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secs -= rtc_dd->offset;
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put_unaligned_le32(secs, value);
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rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
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@ -223,6 +324,7 @@ static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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return rc;
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secs = get_unaligned_le32(value);
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secs += rtc_dd->offset;
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rtc_time64_to_tm(secs, &alarm->time);
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
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@ -378,9 +480,23 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
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rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
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"allow-set-time");
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rtc_dd->nvmem_cell = devm_nvmem_cell_get(&pdev->dev, "offset");
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if (IS_ERR(rtc_dd->nvmem_cell)) {
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rc = PTR_ERR(rtc_dd->nvmem_cell);
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if (rc != -ENOENT)
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return rc;
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rtc_dd->nvmem_cell = NULL;
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}
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rtc_dd->regs = match->data;
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rtc_dd->dev = &pdev->dev;
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if (!rtc_dd->allow_set_time) {
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rc = pm8xxx_rtc_read_offset(rtc_dd);
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if (rc)
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return rc;
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}
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rc = pm8xxx_rtc_enable(rtc_dd);
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if (rc)
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return rc;
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@ -435,3 +551,4 @@ MODULE_ALIAS("platform:rtc-pm8xxx");
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MODULE_DESCRIPTION("PMIC8xxx RTC driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
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MODULE_AUTHOR("Johan Hovold <johan@kernel.org>");
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